Nonvolatile Memory Device FTL Verification Fail Injection
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in efficiently verifying the operation of the flash translation layer (FTL), particularly in accurately identifying and processing failures, which can lead to increased verification time and incorrect classification of memory blocks.
Innovation Solution
Incorporating a fail occurrence register and control logic in the nonvolatile memory device to intentionally cause and manage failures during test operations, allowing for precise verification of FTL functionality by storing fail occurrence information and controlling peripheral circuits to simulate specific failure conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional verification methods are used for FTL operations, then comprehensive failure verification can be achieved, but verification time is excessively long
Solution Approach 1:
The patent applies preliminary action by pre-configuring the fail occurrence register with various failure conditions before FTL verification begins. The control logic is pre-programmed to monitor for these pre-defined failure conditions during operation, allowing the system to immediately detect and report failures without requiring exhaustive testing of all possible failure scenarios, thereby significantly reducing verification time while maintaining comprehensive coverage
Solution Approach 2:
The patent changes the parameter of failure detection from passive observation to active induction by using the fail occurrence register to intentionally trigger specific failure conditions. By modifying the operational parameters through controlled failure injection, the system can verify FTL response to various failure modes much faster than waiting for natural failures or performing exhaustive tests
2Reliability
If exhaustive testing is performed to verify all failure types, then comprehensive failure coverage is achieved, but device complexity and testing overhead increase
Solution Approach 1:
The patent segments the failure verification process into distinct, manageable components by dividing different failure types into separate entries in the fail occurrence register. Each failure condition (read failure, program failure, erase failure, etc.) is independently configured and tested, allowing systematic verification without requiring complex integrated testing procedures for all failures simultaneously
Solution Approach 2:
The fail occurrence register serves as an intermediary mechanism between the test controller and the memory device operations. It translates high-level test requirements into specific failure conditions that can be induced during normal operations, simplifying the testing process by providing a clear interface for controlling and monitoring failure scenarios without requiring direct manipulation of memory cell states
Data Source
AI summary
A nonvolatile memory device includes a memory cell array; a peripheral circuit configured to perform an operation corresponding to a command provided from an external device, for the memory cell array; a fail occurrence register configured to store fail occurrence information for intentionally causing an operation fail to occur; and a control logic configured to store the fail occurrence information in the fail occurrence register based on a fail occurrence command received from the external device, control the peripheral circuit to perform a test operation corresponding to a test operation command received from the external device, for the memory cell array, and control the peripheral circuit to cause an intentional fail to occur in the test operation, based on the fail occurrence information.