Memory Array Gap Layout for Uniform Word Line Etching
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Solution Overview
Problem
Conventional lithography processes face challenges in achieving uniformity and consistency in memory device fabrication due to the loading effect, leading to inconsistent contours and electrical issues at the center and edge of the array region, which affects the integration density and performance of memory devices.
Innovation Solution
The introduction of a memory device design with specific gap width ratios between word lines, dummy word lines, and select gates, along with a method involving sacrificial layers and gap walls to control etching processes, ensuring uniformity and reducing the loading effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If self-aligning double patterning method is used to improve integration density, then manufacturing precision is improved, but loading effect causes inconsistent contours at center and edge
Solution Approach 1:
The patent introduces dummy word lines specifically at the edge regions where pattern density is low, creating a non-uniform distribution of conductive layers. This local modification equalizes the etching load across center and edge regions, ensuring consistent contour formation while maintaining the high integration density achieved through double patterning.
Solution Approach 2:
The dummy word lines are formed as part of the initial patterning process before the final etching step. By pre-establishing these additional structures, the patent ensures that the etching process encounters uniform pattern density throughout the array region, preventing contour inconsistency from developing during fabrication.
2Productivity
If conventional lithography is used to reduce critical dimensions, then productivity is maintained, but resolution approaches theoretical limit
Solution Approach 1:
The patent divides the patterning process into two separate lithography steps (double patterning), where each step forms half of the final pattern. This segmentation allows each lithography step to operate at relaxed resolution requirements while achieving the overall fine pitch needed for high-density memory, maintaining productivity without hitting the theoretical resolution limit of single-step lithography.
Data Source
AI summary
A memory device includes a substrate, a plurality of word lines, a select gate, and a dummy word line. The word lines are located above the substrate. The select gate is located on one side of the word lines. The dummy word line is located between the word lines and the select gate. A first gap between the word lines has a first gap width. A second gap between the dummy word line and an edge word line of the word lines has a second gap width. A third gap between the dummy word line and the select gate has a third gap width. A ratio of the third gap width to the first gap width is between 0.95 and 1.05.