Non-Volatile Memory Garbage Collection Using Mapping Sub-Table Scans

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Solution Overview

Problem

Existing non-volatile memory systems face inefficiencies in garbage collection due to the large size of logical-to-physical address mapping tables and the need to repeatedly download and scan these tables, leading to high computing resource consumption and slowed reading speeds.

Innovation Solution

A non-volatile memory controller that performs a full scan of logical-to-physical address mapping sub-tables to identify and collect valid data efficiently, using a valid data count table and scan flags to optimize garbage collection, prioritizing blocks with low valid data counts for rapid clearing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the system downloads and scans logical-to-physical address mapping tables to identify valid data during garbage collection, then valid data can be identified and collected, but computing resource consumption increases and reading speeds slow down

Engineering Contradiction:
Improvevalid data identification accuracyVSAvoidcomputing resource consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent divides the address mapping table into multiple sub-tables, each corresponding to a specific range of logical addresses. During garbage collection, only the sub-tables relevant to the current source block are downloaded and scanned, rather than the entire address mapping table. This segmentation reduces the amount of data that needs to be processed, thereby lowering computing resource consumption while maintaining accurate valid data identification.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the system repeatedly downloads and scans logical-to-physical address mapping tables during garbage collection, then valid data can be collected, but the garbage collection process slows down

Engineering Contradiction:
Improvevalid data collection completenessVSAvoidgarbage collection speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent pre-loads and caches the logical-to-physical address mapping sub-tables into the controller's memory before the garbage collection process begins. This preliminary action ensures that when garbage collection needs to access mapping information, the data is already available in fast memory rather than requiring repeated downloads from the non-volatile memory, thereby significantly accelerating the garbage collection speed while ensuring complete valid data collection.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the system scans the entire logical-to-physical address mapping table to identify valid data, then all valid data can be found, but the scanning time and computing resources increase

Engineering Contradiction:
Improvevalid data detection completenessVSAvoidscanning time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality by making different parts of the address mapping system have different functions. Specifically, the system downloads only the specific sub-tables that correspond to the logical address ranges of the source blocks being garbage collected, rather than scanning the entire address mapping table. This localized approach reduces scanning time and computing resource usage while ensuring that all relevant valid data is detected through targeted scanning of the appropriate sub-tables.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12579064B2Non-volatile memory controller and control method with improved garbage collection technology
Publication Date: 2026.03.17 SILICON MOTION INC
  • US12579064B2 patent drawing
  • US12579064B2 patent drawing
  • US12579064B2 patent drawing

AI summary

Garbage collection technology for non-volatile memory is shown. The processor starts valid data determination from a starting source block, selects a first logical-to-physical address mapping sub-table corresponding to a first valid data in the starting source block as a scan target, and scans the scan target to identify and collect valid data to be programmed to a destination block. After a full scan of the scan target, the processor checks the starting source block to obtain second valid data that has not yet been collected and programmed to the destination block. The processor selects a second logical-to-physical address mapping sub-table that corresponds to the second valid data as the new scan target. The processor scans the new scan target to collect and program valid data to the destination block. Every time a logical-to-physical address mapping sub-table is downloaded into the controller's memory, it is fully scanned.