3D Non-Volatile Memory Gate-All-Around Structure
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Solution Overview
Problem
Three-dimensional non-volatile memory devices face interference issues between vertically stacked memory cells, degrading device characteristics due to the proximity of adjacent memory cells.
Innovation Solution
The solution involves stacking control gates and interlayer insulating layers on a substrate, with sub-control gates interposed between them, and a common node penetrating these layers to minimize interference by applying a uniform voltage to sub-control gates, which are stepwise patterned to form a gate-all-around structure for memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked vertically in three-dimensional structure, then integration density is improved, but interference between adjacent memory cells increases
Solution Approach 1:
A common node is introduced as an intermediary structure that penetrates through interlayer insulating layers and sub-control gates. This common node serves as a mediator to apply uniform voltage to sub-control gates, thereby reducing the harmful interference between vertically adjacent memory cells while maintaining the high integration density of the 3D structure.
Solution Approach 2:
The voltage distribution parameter is changed by introducing the common node structure. By penetrating through multiple layers and connecting to sub-control gates, the common node enables uniform voltage application across vertically stacked memory cells, transforming the non-uniform electric field into a uniform one to minimize interference.
2Object-affected harmful factors
If sub-control gates are added between control gates and interlayer insulating layers, then interference between memory cells is reduced, but device complexity increases
Solution Approach 1:
The common node performs multiple functions simultaneously: it penetrates through interlayer insulating layers, connects to sub-control gates, applies uniform voltage to reduce interference, and integrates with the existing control gate structure. This multi-functionality reduces the need for separate interference-mitigation structures, thereby limiting the increase in device complexity.
3Manufacturing precision
If common node penetrates interlayer insulating layers and sub-control gates, then uniform voltage application is achieved, but manufacturing complexity increases
Solution Approach 1:
The common node is formed to penetrate through interlayer insulating layers and sub-control gates during the preliminary manufacturing stages. By pre-establishing this penetration structure before final assembly, the uniform voltage application capability is built into the device architecture, reducing the need for complex post-manufacturing adjustments.
Data Source
AI summary
In a semiconductor memory device, a plurality of control gates is stacked in a first region and a second region of a substrate. A plurality of interlayer insulating layers is stacked in a portion of the second region of the substrate. Each interlayer insulating layer is formed at the same level as a corresponding one of the control gates. A plurality of sub-control gates is stacked in the first and second regions region of the substrate and interposed between the control gates and the interlayer insulating layers. A common node penetrates the interlayer insulating layers and the sub-control gates.