3D Memory Gate Contact Structure for Self-Aligned Bonding
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Solution Overview
Problem
Current semiconductor memory devices face challenges in improving operational reliability and manufacturing efficiency due to complexities in the bonding structure and contact formation between the memory cell array and peripheral circuit, particularly in three-dimensional configurations.
Innovation Solution
The semiconductor memory device incorporates a bonding structure with a gate contact structure that includes a vertical and horizontal part, where the gate conductive pattern is spaced apart from the vertical part and extends to surround the channel structure, and a dummy stack structure with a vertical contact structure penetrating both structures to connect with the peripheral circuit layer, simplifying the bonding process and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a bonding structure is introduced to connect the memory cell array and peripheral circuit in three-dimensional configuration, then the degree of integration is improved, but the complexity of the bonding structure increases leading to potential bonding failures
Solution Approach 1:
The patent introduces a bonding structure as an intermediary component between the memory cell array and peripheral circuit. This bonding structure includes a bonding pad structure with contact holes and conductive plugs that mediate the electrical connection, allowing three-dimensional integration while managing the complexity through a standardized interface layer
Solution Approach 2:
The bonding structure is segmented into distinct functional layers: bonding pad structure, contact holes, conductive plugs, and gate contact structures. This segmentation allows each component to be optimized independently and simplifies the overall bonding process by dividing the complex connection task into manageable segments
2Ease of manufacture
If conventional contact formation methods are used to connect gate conductive patterns, then manufacturing simplicity is maintained, but alignment precision and bonding reliability deteriorate
Solution Approach 1:
The gate contact structure is designed to self-align with the gate conductive pattern through the bonding process. The contact hole and conductive plug are positioned such that they automatically align with the gate conductive pattern during bonding, eliminating the need for complex external alignment procedures while maintaining high precision
Solution Approach 2:
The bonding structure is prepared in advance with pre-formed contact holes and conductive plugs positioned at specific locations. This preliminary preparation ensures that when the bonding occurs, the alignment is already established, improving both manufacturing precision and reliability without adding complexity to the actual bonding step
3Productivity
If the gate conductive pattern is directly connected to the gate contact structure, then manufacturing steps are reduced, but bonding reliability may be compromised due to direct contact complexities
Solution Approach 1:
A conductive plug serves as an intermediary element between the gate conductive pattern and the gate contact structure. This plug is formed within the contact hole and provides a reliable electrical connection while physically separating the gate conductive pattern from the external contact structure, thereby maintaining bonding reliability
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes: a peripheral circuit layer; a bonding structure disposed on the peripheral circuit layer; a channel structure disposed on the bonding structure; a first gate contact structure including a first vertical part penetrating the bonding structure and a first horizontal part intersecting with the first vertical part and extending from the first vertical part; and a first gate conductive pattern in contact with a side all of the first horizontal part, the first gate conductive pattern being spaced apart from the first vertical part, the first gate conductive pattern extending to surround the channel structure.