3D Memory Gate Contact Layout for Shallower Via Etching
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Solution Overview
Problem
The increasing etching depth of contact vias in three-dimensional memory structures poses higher requirements for the etching process, leading to significant process difficulty, device damage, and reduced structural stability.
Innovation Solution
A semiconductor structure with distinct sizes for first and second contact structures perpendicular to the stacking direction, utilizing self-aligned contact structures to connect gate layers, and a manufacturing method involving separate processes for forming these structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stack layers is increased to increase storage density, then the storage capacity is improved, but the etching depth of contact vias increases leading to higher process difficulty and reduced structural stability
Solution Approach 1:
The patent divides the contact structure formation into two separate processes: a first process for forming contact structures in the boundary region connecting to the first gate layer, and a second process for forming contact structures in the second region connecting to second gate layers. This segmentation reduces the etching depth requirement for each individual process while achieving the same overall functionality, thereby resolving the technical contradiction between increased storage density and reduced process difficulty.
2Reliability
If the etching depth of contact vias is increased to reach deeper gate layers, then the connectivity to lower gate layers is improved, but device damage increases and structural stability decreases
Solution Approach 1:
The contact structures are segmented into first contact structures in the boundary region and second contact structures in the second region, each formed by separate processes. This allows shallower etching depths for each contact structure compared to a single deep etch process, reducing device damage while maintaining reliable connectivity to respective gate layers.
Solution Approach 2:
The patent applies different contact structure configurations to different regions: the boundary region uses first contact structures with specific size characteristics, while the second region uses second contact structures with different size characteristics. This local differentiation optimizes each region's connectivity requirements while minimizing overall device damage.
3Manufacturing precision
If the contact structure size is made larger to improve manufacturing precision, then the etching alignment is improved, but the area occupied by contacts increases reducing memory density
Solution Approach 1:
The patent implements different contact structure sizes in different regions: first contact structures in the boundary region have one size characteristic, while second contact structures in the second region have different size characteristics. This local quality differentiation allows optimization of etching alignment precision in each region without uniformly increasing the total contact area, thereby maintaining memory density while improving manufacturing precision.
Data Source
Figure 1~2B
Figure 2C~2D
Figure 2E~3
AI summary
The present application provides a semiconductor structure and a manufacturing method thereof, and a memory system. The semiconductor structure includes: a stack structure including a first region, a second region and a boundary region between the first region and the second region, wherein the stack structure includes gate layers and insulation layers stacked alternately, and the gate layers include a first gate layer and a plurality of second gate layers on a side of the first gate layer; a first contact structure in the boundary region, extending and connected to the first gate layer; and a plurality of second contact structures in the second region, extending and connected to the second gate layers of different layers respectively, wherein a size of the first contact structure perpendicular to a stacking direction of the stack structure is different from sizes of the second contact structures perpendicular to the stacking direction.