Non-Volatile Memory Gate Structure for Lower Contact Resistance
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing contact resistance and minimizing the number of lithography operations while manufacturing semiconductor devices with non-volatile memory cells and peripheral logic circuits, particularly due to height differences in interlayer dielectric layers between these areas, which affect chemical mechanical polishing and require additional processing steps.
Innovation Solution
A method is introduced where a substrate is etched to create a step between non-volatile memory cell and peripheral logic circuit areas before forming interlayer dielectric layers, allowing for the formation of isolation layers and planarization, and subsequently, the use of metal material for control gates and conductive layers to reduce resistance and minimize lithography operations by avoiding dummy structures at the transition area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional manufacturing processes are used without substrate etching, then the manufacturing process is simpler, but height differences in interlayer dielectric layers cause increased contact resistance and require additional lithography operations
Solution Approach 1:
The substrate is etched to create a step structure before forming the interlayer dielectric layers. This preliminary action pre-compensates for the height difference that would otherwise require additional lithography operations and causes contact resistance issues, allowing the dielectric layers to be formed uniformly across both memory cell and logic circuit areas.
2Manufacturing precision
If dummy structures are used at the transition area, then manufacturing uniformity is maintained, but the number of lithography operations increases
Solution Approach 1:
By etching the substrate in advance to create the step structure, the patent eliminates the need for dummy structures at the transition area. This preliminary preparation allows uniform dielectric layer formation without requiring additional lithography operations to add or remove dummy features.
3Manufacturing precision
If metal material is used for control gates and conductive layers, then contact resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of metal control gates and metal conductive layers into a single simultaneous deposition process. This combining of operations reduces manufacturing complexity compared to forming these metal structures in separate sequential steps, while still achieving the benefit of reduced contact resistance through the use of metal materials.
Data Source
AI summary
A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.