Memory Gate Contact Structure for Low-Resistance Interconnects
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Solution Overview
Problem
The increasing miniaturization of discrete circuit patterns in highly integrated semiconductor elements complicates the process of forming wiring lines and contacts between them, leading to challenges in contact area and resistance.
Innovation Solution
The semiconductor memory device incorporates a gate structure with multiple conductive layers and a capping layer, featuring spacers on sidewalls and contacts that extend through the capping layer, with varying widths to enhance contact area and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If discrete circuit patterns are miniaturized to increase integration density, then the number of semiconductor elements per area increases, but the contact area between wiring lines and contacts decreases leading to increased resistance
Solution Approach 1:
The contact structure transitions from a conventional planar contact to a multi-dimensional structure that extends vertically through multiple conductive layers. The contact reaches through the capping layer and makes contact with intermediate conductive layers, utilizing the vertical dimension to increase contact area without expanding the horizontal footprint, thus maintaining high integration density while improving contact reliability.
Solution Approach 2:
The contact structure is nested within the gate structure, with the contact extending through the capping layer and making contact with intermediate conductive layers that are themselves nested within the gate structure. This nested arrangement allows the contact to access multiple conductive layers without disrupting the overall gate structure integrity, increasing contact area while maintaining compact design.
2Reliability
If the contact area is increased to reduce resistance, then contact reliability improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The capping layer is formed to cover the gate structure before the contact is formed. This preliminary action of capping protects the gate structure during subsequent processing steps and provides a defined starting point for contact formation. The contact then penetrates through this pre-formed capping layer to reach the intermediate conductive layers, simplifying the overall manufacturing sequence.
Solution Approach 2:
The gate structure is segmented into multiple conductive layers (first, second, and third conductive layers) with different materials, allowing the contact to selectively contact specific intermediate layers. This segmentation enables the contact to achieve increased contact area by accessing multiple discrete conductive layers rather than relying on a single large contact area, thereby reducing resistance without proportionally increasing structural complexity.
Data Source
AI summary
A semiconductor memory device may include a substrate including a cell region and a peripheral region defined around the cell region, and a gate structure which may include sequentially stacked first, second, and third conductive layers including different materials, the first conductive layer including polysilicon. A capping layer may be on the third conductive layer, and a spacer may be on a sidewall of each of the first to third conductive layers and the capping layer. A first contact may extend through the capping layer and into the third conductive layer, with the first contact in contact with the second conductive layer, and separated from the first conductive layer. The first contact may include a first portion in the third conductive layer and a second portion in the capping layer. A width of the first portion may be greater than a width of the second portion in a horizontal direction.