3D Memory Gate Stack Contact Structure to Reduce Voids and Seams
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Solution Overview
Problem
The operational reliability of three-dimensional semiconductor memory devices is compromised due to the complexity of their structure and manufacturing processes, leading to potential issues with the connection and integration of conductive layers and insulating layers.
Innovation Solution
A semiconductor memory device design featuring a gate stack structure with alternately stacked interlayer insulating and conductive layers, a tubular insulating layer penetrating the stepped structure, and a conductive gate contact with a protrusion part that extends between tubular insulating patterns to connect conductive layers, improving integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If various techniques are developed to simplify the structure and manufacturing process of three-dimensional semiconductor memory devices, then the device complexity is reduced, but the operational reliability deteriorates
Solution Approach 1:
The gate contact structure is segmented into multiple components: a tubular insulating layer, a conductive gate contact with a protrusion part, and a conductive layer. This segmentation allows each component to perform its specific function optimally while maintaining overall reliability without excessive complexity
Solution Approach 2:
The protrusion part of the conductive gate contact acts as an intermediary element that bridges the tubular insulating layer and the conductive layer, ensuring reliable electrical connection while maintaining the simplified overall structure
2Adaptability or versatility
If the gate stack structure uses alternately stacked interlayer insulating layers and conductive layers with stepped structure, then the integration is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The design transitions from a planar structure to a three-dimensional stepped structure with tubular insulating layers extending vertically. This dimensional change enables better integration of multiple conductive layers while the standardized tubular geometry simplifies manufacturing compared to complex planar patterning
Solution Approach 2:
The tubular insulating layer is nested within the stepped structure formed by alternately stacked interlayer insulating layers and conductive layers. This nesting arrangement allows efficient use of vertical space for integration while maintaining clear manufacturing boundaries for each layer
3Reliability
If the tubular insulating layer penetrates the stepped structure to connect conductive layers, then the connection between conductive layers is enhanced, but the voids and seams in the tubular insulating layers increase
Solution Approach 1:
The parameters of the tubular insulating layer are optimized, including its thickness, length, and positioning, to ensure it fully penetrates the stepped structure and makes reliable contact with conductive layers while minimizing the formation of voids and seams during the manufacturing process
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device may include a gate stack structure having a stepped structure, which includes a plurality of interlayer insulating layers and a plurality of conductive layers, a tubular insulating layer penetrating the stepped structure of the gate stack structure, and a conductive gate contact connected to an end portion of one of the plurality of conductive layers, the conductive gate contact extending to a central region of the tubular insulating layer.