Programmable Memory Device Gate Coupling Area Control
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Solution Overview
Problem
Precise control of programming voltage in anti-fuse type one-time-programmable (OTP) memory devices is challenging, especially when scaling down, due to susceptibility to lithography and etching inaccuracies, which affects the gate coupling area and threshold voltage of the access transistor.
Innovation Solution
The programmable memory device design includes an active region with a linear top view shape and a gate structure intersecting a section away from the end portions, along with an anti-fuse storage unit using a dielectric layer sandwiched between the active region and an electrode, allowing better control of the gate coupling area and threshold voltage by avoiding the use of end portions as gate coupling regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the gate structure is positioned to intersect with the active region, then the gate coupling area is increased, but the threshold voltage becomes more sensitive to lithography and etching inaccuracies
Solution Approach 1:
The active region is segmented into end portions and a middle section. The gate structure intersects only with the middle section, separating the gate coupling function from the end portions that are susceptible to manufacturing variations. This segmentation allows the gate coupling area to be well-defined while isolating it from lithography and etching inaccuracies affecting the end portions.
Solution Approach 2:
Different regions of the active region are assigned different functions: the end portions are dedicated to anti-fuse storage unit connections, while the middle section is dedicated to gate coupling. This local quality differentiation ensures that the gate coupling area has consistent manufacturing characteristics without being affected by variations at the end portions.
2Productivity
If the device is scaled down, then the integration density is improved, but the programming voltage control becomes more challenging
Solution Approach 1:
By segmenting the active region and positioning the gate structure to intersect only with the middle section, the design creates well-defined geometric boundaries that are less sensitive to scaling effects. This segmentation maintains manufacturing precision for programming voltage control even as device dimensions are reduced to improve integration density.
3Ease of manufacture
If the gate structure intersects with the end portions of the active region, then the manufacturing process is simplified, but the gate coupling area becomes susceptible to lithography and etching inaccuracies
Solution Approach 1:
The active region is divided into end portions and a middle section, with the gate structure specifically positioned to intersect only the middle section. This segmentation maintains ease of manufacture through standard fabrication processes while improving manufacturing precision by excluding the gate coupling area from regions affected by lithography and etching inaccuracies at the end portions.
Data Source
AI summary
The present application provides a programmable memory device. The programmable memory device includes: an access transistor, comprising an active region formed in a substrate and a gate structure formed on the substrate, wherein the active region has a linear top view shape, the gate structure has a first portion and a second portion, the first portion is intersected with a section of the active region away from end portions of the active region, and the second portion is laterally spaced apart from the active region; and a capacitor, using a portion of the active region as a terminal, and further comprising an electrode and a dielectric layer, wherein the electrode is disposed on the portion of the active region and spaced apart from the gate structure, and at least a portion of the dielectric layer is sandwiched between the electrode and the portion of the active region.