3D Memory Gate Electrode Structure With Dual-Resistivity Layers
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Solution Overview
Problem
The increasing complexity of memory devices due to higher integration and electrical connection demands requires improved electrical characteristics and reliability, particularly in semiconductor devices with complex operational circuits and wiring structures.
Innovation Solution
A semiconductor device design featuring a plurality of gate electrodes and insulating layers with specific conductive layers of varying resistivity, including a first conductive layer surrounding channel structures and a second conductive layer with lower resistivity, such as copper or aluminum, to enhance conductivity and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If higher integration and multi-functionalization are implemented to increase capacity, then memory device capacity and integration are improved, but operational circuits and wiring structures become increasingly complex
Solution Approach 1:
The patent transitions from planar 2D memory cell structures to vertically stacked 3D structures with multiple conductive layers arranged in the vertical dimension. This allows higher integration capacity while maintaining simplified wiring by utilizing the third dimension for stacking memory cells and conductive layers, thereby reducing the complexity of lateral wiring structures.
Solution Approach 2:
The patent employs composite conductive structures with multiple layers of different conductive materials (e.g., tungsten, copper, aluminum, cobalt) with varying resistivity values. This composite approach optimizes electrical characteristics by placing low-resistivity materials in critical current paths while using high-resistivity materials for structural stability and isolation, thus improving performance without increasing structural complexity.
2Reliability
If more conductive layers are added to improve electrical connection, then electrical conductivity is improved, but device structure becomes more complex
Solution Approach 1:
The patent applies local quality by assigning different materials and resistivity values to specific conductive layers based on their functional requirements. Low-resistivity materials (copper, aluminum) are placed in layers requiring high current carrying capacity, while high-resistivity materials (tungsten, cobalt) are used in layers requiring structural support or electrical isolation. This localized optimization improves electrical connection reliability without requiring uniform complexity throughout the entire structure.
Solution Approach 2:
The patent systematically varies the resistivity parameter across different conductive layers by selecting materials with appropriately different resistivity values. This parameter change strategy allows optimization of electrical characteristics for different functional regions while maintaining a manageable layered structure, balancing improved electrical connection with controlled structural complexity.
3Speed
If resistance is reduced to improve response speed, then response speed is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses composite conductive layers with materials of different resistivity values to achieve overall low resistance while accommodating manufacturing variations. The combination of materials provides tolerance to dimensional variations and deposition thickness variations, reducing the impact of manufacturing precision limitations on final resistance values while still achieving improved response speed.
Solution Approach 2:
The patent changes material parameters (resistivity, thickness, width) across different conductive layers to optimize resistance while accounting for manufacturing capabilities. By selecting materials with appropriate resistivity ranges and designing layer dimensions that are robust to manufacturing variations, the patent achieves low resistance for improved speed without excessively stringent precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the reliability and response speed of semiconductor devices by reducing resistance by up to 53% and RC delay by 15%, maintaining high integration levels even in triple or quadruple level cells.
Implementation Method 1
resistivity of the second conductive layer is less than the resistivity of the first conductive layer
Implementation Method 2
a conductive barrier layer arranged between the first conductive layer and the second conductive layer
Data Source
AI summary
Provided is a semiconductor device. The semiconductor device includes: a plurality of insulating layers and a plurality of gate electrodes alternately arranged in a first direction; and a plurality of channel structures passing through the plurality of gate electrodes and the plurality of insulating layers in the first direction, wherein each of the plurality of gate electrodes includes: a first conductive layer including an inner wall surrounding the plurality of channel structures; and a second conductive layer that is separated from the plurality of channel structures in a second direction perpendicular to the first direction, wherein resistivity of the second conductive layer is less than resistivity of the first conductive layer.