3D Nonvolatile Memory Gate Electrode Void Reduction
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Solution Overview
Problem
Conventional 3D nonvolatile memory devices face issues with increased resistance in word lines due to voids formed during the etching process, leading to a smaller volume at the top and potential electrical bridges, which affect the performance and reliability of the memory cells.
Innovation Solution
The method involves alternately stacking interlayer dielectric and sacrificial layers, forming channel and slit holes, removing sacrificial layers to create spaces for gate electrode layers, and using a second gate electrode layer to protrude from the interlayer dielectric layers, thereby increasing the volume of the gate electrode layer and reducing resistance without forming electrical bridges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the etching process is used to form word lines by removing sacrificial layers, then the gate electrode structure can be formed, but voids are created in the word line leading to increased resistance
Solution Approach 1:
A plug structure is formed in advance at the top of the channel layer before the word lines are created. This preliminary structure serves as a foundation that prevents void formation when sacrificial layers are removed, thereby maintaining low resistance in the gate electrode while still enabling the etching-based formation process
Solution Approach 2:
The plug acts as an intermediary structure between the channel layer and the gate electrode. It provides mechanical support and electrical continuity, preventing the formation of voids that would otherwise occur during the removal of sacrificial layers, thus resolving the contradiction between ease of manufacture and reliability
2Device complexity
If the top word line is etched more than the bottom word line, then the gate electrode structure is formed, but the top volume decreases leading to higher resistance
Solution Approach 1:
The plug structure provides localized support at the top of the channel layer where the gate electrode would otherwise be most vulnerable to excessive etching. This local reinforcement ensures uniform etching across all word lines while maintaining the necessary three-dimensional gate structure, preventing top volume reduction and associated resistance increases
3Ease of manufacture
If excessive etching is performed to open the word line, then the structure is simplified, but the word line may open completely causing resistance to increase rapidly
Solution Approach 1:
The plug structure serves as a cushioning element that prevents the gate electrode from being completely etched away. Even when excessive etching occurs during the formation process, the plug maintains structural integrity and electrical continuity, preventing complete opening of the word line and the associated rapid resistance increase
Data Source
AI summary
A nonvolatile memory device includes a substrate including a surface, a channel layer formed on the surface of the substrate, which protrudes perpendicularly from the surface, and a plurality of interlayer dielectric layers and a plurality of gate electrode layers alternately stacked along the channel layer, wherein the plurality of gate electrode layers protrude from the plurality of interlayer dielectric layers.