Memory Gate Structure With Protruding Portion for Better Erase Current
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Solution Overview
Problem
Existing memory devices face challenges in improving their electrical performance, particularly in terms of on-current and erasing capability.
Innovation Solution
A memory structure is designed with a gate that has a protruding portion located between two adjacent charge storage layers, enhancing the electrical performance by improving on-current and erasing capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate structure is used, then the device complexity is low, but the on-current and erasing capability are insufficient
Solution Approach 1:
The gate is segmented into multiple portions (first gate portion, second gate portion, third gate portion) with different configurations. The second gate portion extends in the first direction while the first and third gate portions extend in the second direction, creating a segmented structure that improves erasing capability without excessive complexity
Solution Approach 2:
Different portions of the gate have different local configurations optimized for specific functions. The second gate portion is positioned to enhance on-current, while the first and third gate portions are positioned to improve erasing capability, applying local quality variations to achieve global performance improvement
2Reliability
If the gate structure is modified to improve on-current, then the electrical performance improves, but the manufacturing precision requirements increase
Solution Approach 1:
The gate structure employs asymmetric configuration where the second gate portion extends in the first direction with different dimensions compared to the first and third gate portions extending in the second direction. This asymmetric design improves on-current while maintaining manufacturability through clear dimensional differentiation
Solution Approach 2:
The gate structure utilizes two-dimensional extension (first direction and second direction) to create multiple gate portions. This dimensional approach allows improvement of on-current through increased gate coverage area without requiring extremely tight alignment tolerances in a single dimension
Data Source
AI summary
A memory structure including a substrate, charge storage layers, and a gate is provided. The charge storage layers are located on the substrate. The gate is located on the substrate on one side of the charge storage layers. The gate extends along a first direction. The gate has a protruding portion protruding along a second direction. The second direction intersects the first direction. The protruding portion is located between two adjacent charge storage layers arranged along the first direction.