Semiconductor Memory Gate Structure for Fluorine Leak Suppression

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Solution Overview

Problem

Current semiconductor memory devices face issues with leak currents due to the diffusion of fluorine from conductive layers into insulating films, leading to voids and reduced reliability.

Innovation Solution

The formation of silicon layers on the upper surfaces of interlayer insulating layers within the conductive layers, which helps to maintain silicon content and reduce fluorine diffusion, thereby minimizing leak currents and enhancing device performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If fluorine-containing conductive layers are used to improve conductivity, then electrical conductivity is improved, but fluorine diffuses into insulating films causing voids and increased leak currents

Engineering Contradiction:
Improveelectrical conductivityVSAvoidleak current
Core Design Contradiction:
PowerVSReliability

Solution Approach 1:

A silicon layer is introduced as an intermediary barrier between the fluorine-containing conductive layer and the insulating film. This silicon layer prevents fluorine diffusion into the insulating film while allowing the conductive layer to maintain its electrical conductivity function.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The conductive layer structure is segmented into multiple regions with different silicon contents. The first region (near the insulating film) has higher silicon content to prevent fluorine diffusion, while the second region (deeper in the conductive layer) has lower silicon content to maintain conductivity, creating a functional gradient structure.

Inventive Principle:
Principle #1Segmentation

2Reliability

If silicon content is increased in conductive layers to prevent fluorine diffusion, then fluorine diffusion is reduced, but electrical conductivity decreases

Engineering Contradiction:
Improvefluorine diffusion resistanceVSAvoidelectrical conductivity
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

Different regions of the conductive layer are assigned different silicon contents based on their functional requirements. The region adjacent to the insulating film has high silicon content for fluorine barrier function, while the region deeper in the conductive layer has low silicon content for electrical conductivity function.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The silicon content parameter is varied spatially within the conductive layer to optimize both fluorine diffusion resistance and electrical conductivity. By controlling the silicon concentration gradient, the structure achieves optimal performance for both conflicting requirements.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces leak currents and improves the operational stability of semiconductor memory devices by maintaining higher silicon content in critical regions, thus extending charge and discharge times and maintaining an optimal electric field across the gate insulating film.

Implementation Method 1

The formation of silicon layers on the upper surfaces of interlayer insulating layers within the conductive layers, which helps to maintain silicon content and reduce fluorine diffusion

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS11915928B2Semiconductor memory device and method of manufacturing the same
Publication Date: 2024.02.27 KIOXIA CORP
  • US11915928B2 patent drawing
  • US11915928B2 patent drawing
  • US11915928B2 patent drawing

AI summary

A semiconductor memory device includes a first conductive layer, a semiconductor layer extending in a first direction and being opposed to the first conductive layer, and a gate insulating film disposed between the first conductive layer and the semiconductor layer. The first conductive layer includes a first region, a second region disposed between the first region and the gate insulating film, and a third region disposed between the first region and the first interlayer insulating layer. The first to the third regions contain a metal. The third region contains silicon (Si). The first region does not contain silicon (Si) or has a lower silicon (Si) content than a silicon (Si) content in the third region. The second region does not contain silicon (Si) or has a lower silicon (Si) content than the silicon (Si) content in the third region.