Memory Cell Gate Gap Filling for Stable Air Gap Structure

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Solution Overview

Problem

The reduction in component dimensions during the manufacturing of memory devices, such as flash memory, leads to excessive air gaps between select gate and word line structures, affecting performance and structural strength, resulting in defects and electrical issues.

Innovation Solution

A method involving the formation of a filling material to cover the select gate and word line structures, followed by etching back processes to expose specific areas, application of a cap layer and dielectric layers, and removal of the filling material to create a protruding cap layer portion, with a second dielectric layer filling the gaps to maintain structural integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the dimensions of components are continuously scaled down, then the productivity and integration density are improved, but the air gap between select gate structure and word line structures becomes excessive, worsening the structural strength and performance

Engineering Contradiction:
Improveintegration densityVSAvoidstructural strength
Core Design Contradiction:
ProductivityVSStrength

Solution Approach 1:

A filling material is formed in advance between the select gate structure and word line structures before final dielectric layer formation. This preliminary filling action prevents excessive air gap formation that would occur with continued dimension scaling, thereby maintaining structural strength while allowing continued miniaturization for improved productivity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The filling material acts as an intermediary substance between the select gate structure and word line structures. This intermediary material fills the space that would otherwise be an air gap, providing mechanical support and maintaining structural integrity as components are scaled down to improve integration density

Inventive Principle:
Principle #24Intermediary (Mediator)

2Strength

If the air gap between select gate structure and word line structures is reduced, then the structural strength is improved, but the manufacturing process complexity increases due to additional filling and etching steps

Engineering Contradiction:
Improvestructural strengthVSAvoidmanufacturing process complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The formation of the filling material is merged with the existing dielectric layer formation process. The filling material is deposited conformally along with the inter-gate dielectric layer, and subsequent etching steps that remove excess dielectric material also remove excess filling material. This merging approach reduces manufacturing process complexity while maintaining the structural strength benefits of reduced air gaps

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If the air gap is excessive, then the manufacturing process is simpler, but the performance deteriorates due to increased defects and electrical problems

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidperformance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The physical state and dimensions of the filling material are carefully controlled through parameter changes in the deposition process. By adjusting filling material thickness, composition, and deposition conditions, the air gap is reduced to an optimal range that improves reliability without requiring completely new manufacturing processes, thus maintaining ease of manufacture

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250324588A1Memory device and method for manufacturing the same
Publication Date: 2025.10.16 WINBOND ELECTRONICS CORP
  • US20250324588A1 patent drawing
  • US20250324588A1 patent drawing
  • US20250324588A1 patent drawing

AI summary

A method of manufacturing a memory device includes: providing a substrate, forming a select gate structure and word line structures on the substrate, and forming a filling material to cover the select gate structure and the word line structures. The method includes etching back the filling material to expose the top of the select gate structure and the top of the word line structures, sequentially forming a cap layer and a first dielectric layer over the substrate, and etching back the first dielectric layer and the cap layer to expose the filling material between the select gate structure and the dummy word line in the word line structures that is closest to the select gate structure. The method includes removing the filling material and leaving the protruding portion of the cap layer, and forming a second dielectric layer to cover the first dielectric layer.