Non-Volatile Memory Gate Protection via Hard Mask Segmentation
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Solution Overview
Problem
Conventional methods for manufacturing non-volatile memory devices often damage the control gate during etching processes due to inadequate protection of the floating gate, as both gates are typically protected by a single mask layer, leading to ineffective protection and potential damage to the control gate.
Innovation Solution
A method involving the use of a hard mask layer and photo resist to create differential height/thickness between the control and logic gates, with a protective silicon oxide film and silicon oxynitride layer to protect the floating gate during etching, allowing for the formation of a control gate beside the floating gate and preventing damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single protective mask layer is used to protect both control gate and floating gate during etching, then the manufacturing process is simple, but the control gate is easily damaged due to inadequate protection
Solution Approach 1:
The protective mask layer is divided into two separate layers: a first protective mask layer (silicon oxide) and a second protective mask layer (amorphous carbon). The first layer protects the control gate during logic gate formation, while the second layer provides additional protection during subsequent etching processes. This segmentation allows each layer to be optimized for specific protection needs, resolving the contradiction between manufacturing simplicity and protection reliability.
Solution Approach 2:
The first protective mask layer is formed preliminarily before the logic gate etching process to protect the control gate. This preliminary protective action ensures that the control gate is already protected before the harmful etching process begins, preventing damage while maintaining process efficiency.
2Area of stationary object
If the control gate is located on an upper portion of the floating gate, then the device structure is compact, but the control gate is more vulnerable to damage during etching
Solution Approach 1:
The first protective mask layer (silicon oxide) is deposited beforehand to cushion and protect the control gate from etching damage. This protective layer acts as a buffer between the control gate and the harmful etching process, allowing the control gate to remain in the upper portion for compactness while being protected from damage.
3Ease of manufacture
If photo resist is used as protective mask, then the mask can be easily patterned, but the photo resist may be damaged during etching processes
Solution Approach 1:
The patent combines photo resist with amorphous carbon to form the second protective mask layer. The amorphous carbon provides enhanced durability and resistance to etching processes, while the photo resist component maintains the ease of patterning. This merged structure resolves the contradiction between easy patterning and mask durability during etching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents damage to the floating gate during the etching process for forming the logic gate, ensuring the integrity of both the control and floating gates, and allows for the formation of a higher control gate, enhancing the manufacturing process's precision and reliability.
Implementation Method 1
depositing a protective film on the floating gate... effectively prevents damage to the floating gate during the etching process
Implementation Method 2
depositing a first conductive film and a protective film on the substrate... depositing a hard mask layer on the first conductive film
Data Source
AI summary
A method for manufacturing a non-volatile memory includes depositing a first conductive film and a protective film on a substrate including a logic area and a cell area, patterning the protective film, depositing a hard mask layer on the first conductive film and the patterned protective film to pattern the hard mask layer, using the patterned hard mask layer to form a logic gate on the logic area, exposing a surface of the first conductive film in the cell area and forming a control gate on the cell area.