Memory Gate Stack Masking to Block Ion Penetration
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Solution Overview
Problem
The manufacturing process of flash memory devices often results in charged ions penetrating the gate structure, compromising the reliability of the memory device.
Innovation Solution
A manufacturing method involving the formation of a gate stacking structure with a specific insulating layer and spacer configuration to block charged ions, including a first and second insulating layer and a first spacer, where the top surface and sidewall of the gate stacking structure are covered by the first insulating layer, and the first spacer covers the second insulating layer, effectively preventing ion penetration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional manufacturing process is used for flash memory devices, then the manufacturing process is simple and fast, but charged ions penetrate into the gate structure and compromise reliability
Solution Approach 1:
The gate structure is segmented into multiple distinct layers including a first gate electrode, a second gate electrode, and an inter-gate dielectric layer between them. This segmentation allows each layer to perform specific functions and provides better control over ion penetration paths, thereby improving reliability without excessive complexity
Solution Approach 2:
The patent implements a nested structure where the first gate electrode and second gate electrode are positioned at different heights and depths, with the inter-gate dielectric layer nested between them. This nested arrangement creates multiple barriers against ion penetration while maintaining a compact overall structure
2Ease of manufacture
If the gate structure is simplified for easier manufacturing, then manufacturing complexity is reduced, but the ability to block charged ions during manufacturing is weakened
Solution Approach 1:
The patent applies a preliminary protective action by forming a capping layer over the gate electrode structure before the ion implantation process. This capping layer serves as a preliminary barrier that prevents charged ions from penetrating into the gate structure during subsequent manufacturing steps, thereby protecting the device without complicating the manufacturing process
Solution Approach 2:
The inter-gate dielectric layer acts as an intermediary material between the first gate electrode and the second gate electrode. This intermediary layer not only electrically isolates the two electrodes but also serves as an additional barrier against ion penetration, thus protecting the gate structure while maintaining manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of the memory device by blocking charged ions generated during the manufacturing process, thereby improving the device's operational integrity.
Implementation Method 1
performing an ion implantation process on the mask material layer, to form a doped portion in the mask material layer
Data Source
AI summary
A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.