3D Memory Gate Structure With Mirror-Tapered Contacts
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to enhance the degree of integration and operational reliability, particularly as two-dimensional memory cell formation reaches its limits, necessitating innovative three-dimensional stacking solutions.
Innovation Solution
The semiconductor device employs a gate structure with alternately stacked conductive and insulating layers, featuring tapered supports and contact structures that are 'mirror images' of each other, along with a manufacturing method involving alternative material layers, etch stop layers, and sacrificial supports to create a stable and integrated structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-dimensional memory cell formation is used, then manufacturing process is simpler, but degree of integration reaches a limit
Solution Approach 1:
The patent transitions from two-dimensional memory cell formation to three-dimensional stacking architecture, where memory cells are stacked vertically along the channel length direction. This dimensional change enables higher degree of integration by utilizing the vertical space above the substrate, allowing multiple memory cells to occupy a smaller footprint area while maintaining manufacturability through adapted fabrication processes.
2Productivity
If three-dimensional stacking is implemented, then degree of integration is improved, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming conductive layers and insulating layers alternately stacked, creating supports extending through the gate structure, and forming contact structures between the supports. This segmentation allows complex three-dimensional structures to be built systematically through manageable process steps, reducing overall manufacturing complexity.
Solution Approach 2:
Supports are formed preliminarily to extend through the gate structure before final contact structure formation. These supports serve as pre-positioned structural elements that guide subsequent manufacturing steps and provide mechanical stability during the complex stacking process, simplifying the overall fabrication sequence.
3Ease of manufacture
If conventional manufacturing methods are used, then process is easier to implement, but damage to peripheral layers occurs
Solution Approach 1:
The patent implements localized etching and material removal in specific regions between the supports, rather than uniform processing across the entire structure. This local quality approach allows precise control over where material is removed or modified, preventing damage to peripheral layers while achieving the desired three-dimensional memory cell structure in targeted areas.
4Device complexity
If conventional manufacturing methods are used, then process is simpler, but residual materials remain after manufacturing
Solution Approach 1:
The manufacturing process explicitly extracts and removes residual materials through targeted etching steps that eliminate material between the contact structure and supports, and between the support and peripheral layers. This extraction process ensures complete removal of unwanted residues, achieving cleaner final structures with improved reliability.
Data Source
AI summary
A semiconductor device may include: a gate structure including conductive layers and insulating layers that are alternately stacked. Tapered supports formed in the gate structure layers have a first width at a first level of the layers and a second width smaller than the first width at a second level of the layers. A tapered contact structure is located between the tapered supports in the gate structure having a third width at the first level and a fourth width larger than the third width at the second level. The gate structure taper and the contact structure taper are “mirror images” of each other.