Non-Volatile Memory Gate Oxidation for Void-Free Integration

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Solution Overview

Problem

The challenge in manufacturing non-volatile memory devices is the difficulty in filling the space between memory cells with insulating material without forming voids or missing spaces, due to the limitations of photolithographic and etching processes, which affects the packing density and reliability of the devices.

Innovation Solution

A method involving the formation of an oxide layer on the sidewalls of the first gates through oxidation processes, such as in situ steam generation or thermal oxidation, to serve as a dielectric material that fills the space between memory cells before forming second gates, allowing for controlled thickness and reduced spatial separation between adjacent cells.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If photolithographic and etching processes are used to reduce device dimensions and space between memory cells, then device integration level increases, but the process window limitation makes it difficult to meet required memory cell size and spatial separation

Engineering Contradiction:
Improvedevice integration levelVSAvoidmemory cell size and spatial separation
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The gate structure is divided into first gates and second gates formed at different stages. The first gates are formed initially, then an oxide layer is deposited on their sidewalls, and finally second gates are formed in the spaces between first gates. This segmentation allows independent optimization of each gate component and enables tighter packing while maintaining manufacturing precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An oxide layer is formed on the sidewalls of the first gates before forming the second gates. This preliminary oxidation creates a protective and defining layer that enables precise formation of second gates in the spaces between first gates, ensuring proper spatial separation even at reduced dimensions.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the space between memory cells is reduced to increase packing density, then device integration increases, but voids form in the insulating material layer or the insulating material is prevented from filling the space

Engineering Contradiction:
Improvepacking densityVSAvoidinsulating material filling quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

An oxide layer is formed on the sidewalls of the first gates before filling the spaces with insulating material and forming second gates. This preliminary oxidation creates a surface that facilitates complete filling of the spaces with insulating material, preventing void formation even when spaces are tightly reduced.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The oxide layer acts as an intermediary between the first gates and the insulating material. It provides a suitable surface for insulating material deposition and ensures complete filling of the spaces between memory cells, eliminating voids while maintaining tight packing density.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If insulating material is used to fill the space between memory cells, then device integration increases, but voids form in the insulating material layer reducing process reliability

Engineering Contradiction:
Improvedevice integrationVSAvoidprocess reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

An oxide layer is formed on the sidewalls of the first gates before depositing the insulating material. This preliminary oxidation prepares the surface to ensure complete and void-free filling of the spaces between memory cells, maintaining process reliability while achieving high device integration.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The oxide layer serves as an intermediary layer between the first gates and the insulating material. It ensures proper adhesion and complete filling of the insulating material in the spaces between memory cells, eliminating voids and maintaining high process reliability during integration.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces the formation of voids in the insulating material and improves the reliability of the process by allowing for tighter packing density and increased integration of memory cells, overcoming the limitations of conventional photolithographic and etching processes.

Implementation Method 1

An oxidation process is performed to form an oxide layer on the sidewalls of the first gates

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

the foregoing oxidation process is, for example, an in situ steam generation (ISSG) oxidation process or a thermal oxidation process

Methodology Applied
Scientific EffectThermal oxidation: Oxidation

Data Source

PatentUS7772068B2Method of manufacturing non-volatile memory
Publication Date: 2010.08.10 MACRONIX INTERNATIONAL CO LTD
  • US7772068B2 patent drawing
  • US7772068B2 patent drawing
  • US7772068B2 patent drawing

AI summary

A method of manufacturing a non-volatile memory including the following steps is provided. First, a dielectric layer, a first conductive layer and a patterned mask layer are sequentially formed on a substrate. A portion of the first conductive layer is removed using the patterned mask layer as a mask to form a plurality of first gates. An oxidation process is performed to form an oxide layer on the sidewalls of the first gates. The patterned mask layer is removed. A plurality of second gates is formed between two adjacent first gates so that the first gates and the second gates co-exist to form a memory cell column. A doped region is formed in the substrate adjacent to the memory cell column.