3D Memory Gate Pad Structure for Reliable Select-Line Biasing
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Solution Overview
Problem
The integration density of semiconductor devices is limited by the area occupied by unit memory cells, and existing three-dimensional stacking methods do not adequately address the operational reliability of semiconductor devices.
Innovation Solution
A semiconductor device structure featuring a gate structure with word lines and select lines, including a first pad stepped structure and a common pad structure, allows for contact plugs connected to select lines and common contact plugs, enabling parallel bias application to improve transistor operating speeds and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If three-dimensional stacking methods are used to improve integration density, then the area occupied by unit memory cells is reduced, but the operational reliability of semiconductor devices deteriorates
Solution Approach 1:
The gate structure is segmented into multiple gate lines (first gate line, second gate line, etc.) with dedicated contact plugs for each, allowing independent bias application to different segments. This segmentation enables precise control of electrical characteristics for each gate line while maintaining the three-dimensional stacked structure, thereby improving operational reliability without sacrificing integration density.
Solution Approach 2:
The common pad structure provides a universal connection point that can be shared by multiple contact plugs connected to different gate lines. This multi-functional design allows a single pad structure to serve multiple gate lines simultaneously, reducing the overall area required while maintaining the ability to apply bias independently to each gate line through respective contact plugs.
2Ease of operation
If multiple contact plugs are used to connect to different gate lines, then bias application control is improved, but device complexity increases
Solution Approach 1:
Multiple contact plugs are merged into a single common pad structure, where different contact plugs connect to different gate lines but converge at the shared common pad. This merging reduces structural complexity compared to having completely separate pad structures for each gate line, while still maintaining the ability to apply bias independently to each gate line through its dedicated contact plug.
3Ease of manufacture
If conventional contact structures are used in three-dimensional stacked structures, then manufacturing process is simpler, but resistance is higher and transistor operating speed is slower
Solution Approach 1:
The contact structure implements local quality by providing dedicated contact plugs for each gate line that connect to a common pad structure. This localized connection approach reduces resistance at each contact point compared to conventional shared contact structures, improving transistor operating speed while maintaining manufacturing process simplicity through the standardized common pad formation process.
Data Source
AI summary
A semiconductor device includes a gate structure including word lines and select lines, the gate structure including a first pad stepped structure for exposing each of the select lines and a common pad structure for exposing the select lines. The semiconductor device also includes first contact plugs connected to the select lines through the first pad stepped structure, respectively. The semiconductor device further includes one or more common contact plugs connected in common to the select lines through the common pad structure.