Semiconductor Memory Gate Planarization for Height-Difference Etching
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Solution Overview
Problem
The complexity of semiconductor structures with high-k metal gates leads to significant height differences between areas, resulting in over-processing and the risk of depression during integrated circuit processing.
Innovation Solution
A method involving the formation of a mask layer and patterned photoresist layer followed by selective etching, deposition of an isolation wall, and controlled etching of dielectric layers to maintain a flat surface, using a 1:1 etching rate ratio for silicon oxide to silicon nitride to ensure uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If selective etching is performed on areas with different heights, then the processing can accommodate complex longitudinal structures, but the surface structure may be excessively eliminated resulting in depression
Solution Approach 1:
A planarization layer is formed in advance on the semiconductor structure before subsequent processing steps. This preliminary action creates a flat reference surface that prevents over-etching and depression during later selective etching operations, allowing the process to accommodate complex longitudinal structures while maintaining surface integrity.
Solution Approach 2:
The planarization layer acts as an intermediary between the complex longitudinal structures and the subsequent processing steps. It provides a uniform surface that mediates the etching process, ensuring that etching proceeds uniformly without excessively eliminating surface structures or causing depression in areas with different heights.
2Adaptability or versatility
If the semiconductor structure uses high-k metal gate with different longitudinal structures in different areas, then functional differentiation is achieved, but height differences are enlarged causing processing difficulties
Solution Approach 1:
The planarization layer is deposited in advance to compensate for the height differences created by different longitudinal structures in different areas. This preliminary action maintains the functional differentiation while providing a flat surface for subsequent processing, effectively managing the device complexity.
Solution Approach 2:
Different longitudinal structures are maintained in different areas to achieve functional differentiation, while the planarization layer provides a uniform local quality (flat surface) across all areas for subsequent processing. This allows each area to maintain its specific functional characteristics while the overall surface remains planar.
Data Source
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AI summary
The present disclosure provides a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor memory. The method includes the following operations. An initial semiconductor structure is formed on a substrate. The initial semiconductor structure is etched to form an array area structure and a peripheral area structure including a peripheral area gate structure. An isolation wall surrounding the peripheral area gate structure is formed on the substrate where the peripheral area structure locates. A second dielectric layer is deposited on the peripheral area gate structure including the isolation wall and on the array area structure. The second dielectric layer, the first dielectric layer and the isolation wall are etched to form the semiconductor structure with a flat surface. The invention can avoid excessive elimination of a surface structure and reduce the risk of depression during processing of an integrated circuit.