Memory Transistor Gate Recess Structure for Threshold Voltage Stability

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Solution Overview

Problem

In semiconductor memory devices, the variation in threshold voltage due to corner effects in transistors caused by differences in gate insulating film thickness and corner electric field intensity leads to performance and reliability issues.

Innovation Solution

A semiconductor memory device design featuring a substrate with an active region, element isolation films, and sub-element isolation films, where the gate insulating film extends along the active region and fills recesses, with specific thickness profiles to optimize the gate structure and reduce threshold voltage variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the gate insulating film thickness is reduced to improve transistor scaling, then the device size decreases, but the threshold voltage control becomes poor due to corner electric field effects

Engineering Contradiction:
Improvegate insulating film thicknessVSAvoidthreshold voltage control
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent applies local quality by creating different gate insulating film thicknesses at different locations: the film is thinner at the corner regions and thicker at the center region. This localized thickness variation compensates for the corner electric field effects that cause threshold voltage variations, allowing the transistor to maintain proper threshold voltage control even with overall reduced film thickness for scaling.

Inventive Principle:
Principle #3Local quality

2Reliability

If the gate insulating film thickness is increased to improve threshold voltage control, then the threshold voltage stability improves, but the device size and capacitance increase

Engineering Contradiction:
Improvethreshold voltage stabilityVSAvoidgate insulating film thickness
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The patent uses local quality to provide thicker gate insulating film specifically at the corner regions where electric field intensity is highest, while maintaining thinner film at the center. This localized thickening improves threshold voltage stability at critical corner points without requiring overall increase in film thickness, thus avoiding unnecessary device size and capacitance increases.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If the transistor structure uses uniform gate insulating film thickness, then the manufacturing process is simple, but the threshold voltage varies due to corner effects

Engineering Contradiction:
Improvegate insulating film depositionVSAvoidthreshold voltage uniformity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent implements local quality through a multi-layer gate insulating film structure with different thicknesses at different locations. This can be achieved through selective epitaxial growth or selective deposition techniques, where the film thickness is controlled to be thinner at corners and thicker at the center, improving threshold voltage uniformity while maintaining manufacturing feasibility through established semiconductor fabrication processes.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent transitions from a uniform two-dimensional gate insulating film to a three-dimensional structure with varying thickness across the film area. This dimensional change allows the film to have different thicknesses at different spatial locations, enabling compensation for corner electric field effects while maintaining a continuous film structure that can be manufactured using standard deposition techniques.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240379406A1Semiconductor memory device
Publication Date: 2024.11.14 SAMSUNG ELECTRONICS CO LTD
  • US20240379406A1 patent drawing
  • US20240379406A1 patent drawing
  • US20240379406A1 patent drawing

AI summary

A semiconductor device is disclosed. The semiconductor memory device comprises a substrate including an active region, an element isolation film disposed in the substrate and that defines the active region, a recess which is disposed in the active region and extends in a first direction, and a gate structure extending in a second direction, on the active region, wherein the gate structure includes a gate insulating film, a gate stack pattern, and a gate capping pattern which are sequentially stacked, wherein the gate insulating film extends along an upper face of the active region, and a part of the gate insulating film fills the recess, and wherein a height from a lower face of the substrate to a bottom face of the element isolation film is less than a height from the lower face of the substrate to a bottom face of the recess.