Non-Volatile Memory Gate Spacer Layout to Prevent Silicide Shorts
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Solution Overview
Problem
Non-volatile semiconductor memory devices face a short circuit problem due to the close proximity between the control gate and select gate, which can occur when they are in contact through a silicide layer, leading to cell leakage current issues.
Innovation Solution
The semiconductor device design includes a select gate with a height lower than the control gate silicide layer, with spacers strategically placed between the select gate and control gate silicide layers to maintain a safe distance and prevent short circuits, and the use of spacers on the sidewalls of the gate stack to insulate and separate the select gate from the control gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the select gate is formed adjacent to the control gate to reduce cell leakage current, then cell leakage current is reduced, but the control gate and select gate may contact through silicide layers causing short circuit
Solution Approach 1:
An insulating spacer is introduced as an intermediary element between the control gate and select gate. This spacer physically separates the two gates, preventing direct contact through silicide layers while allowing the gates to remain adjacent for effective leakage current reduction. The spacer acts as a mediator that enables the beneficial proximity effect without the harmful short circuit effect.
Solution Approach 2:
The space between the control gate and select gate is segmented by introducing an insulating spacer structure. This segmentation divides the continuous conductive path that would otherwise exist through silicide layers into separate regions, with the insulating spacer creating a non-conductive barrier that prevents electron flow between the gates.
2Area of stationary object
If the select gate is positioned close to the control gate, then device area is reduced, but manufacturing precision is compromised due to difficulty in preventing short circuits
Solution Approach 1:
The insulating spacer is formed preliminarily before final gate structure completion. By establishing the spacer structure in advance, the minimum separation distance between control gate and select gate is predetermined and fixed, ensuring that subsequent manufacturing steps cannot cause the gates to contact. This preliminary action locks in the precise spacing required for both compact area and reliable manufacturing.
Data Source
AI summary
A semiconductor device includes a first source region and a drain region disposed on a substrate; a first gate stack comprising a first floating gate and a first control gate, and disposed between the first source region and the drain region; a first select gate disposed on one sidewall of the first gate stack; a first spacer disposed on a lower sidewall of the first select gate, and disposed adjacent to the first source region; a second spacer disposed on an upper sidewall of the first select gate; a first control gate silicide layer disposed on the first control gate; and a first select gate silicide layer disposed on the first select gate, and disposed between the first spacer and the second spacer.