Semiconductor Memory Gate Spacing Film Structure
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Solution Overview
Problem
Conventional flash memory devices face challenges in maintaining high breakdown voltage between gates due to the electrical isolation requirements of the dielectric spacing film, which is prone to short circuits.
Innovation Solution
The method involves forming a substrate with gate structures and dielectric caps, followed by the creation of first and second dielectric layers, where the second gates cover and protect the top edges of the first spacing films, thereby maintaining or increasing the breakdown voltage between the gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric spacing film is used to electrically isolate gates, then electrical isolation between gates is achieved, but the breakdown voltage between gates decreases due to short circuit risks
Solution Approach 1:
The patent divides the spacing structure into multiple segments: a first spacing film formed between adjacent gate structures, and a second spacing film formed between the gate structure and the interconnect. This segmentation allows each spacing film to be optimized for its specific function, with the first spacing film providing electrical isolation and the second spacing film providing mechanical support and additional isolation, thereby maintaining high breakdown voltage while ensuring reliable electrical isolation.
Solution Approach 2:
The patent introduces an intermediary structure (the gate structure with its specific configuration and the combined spacing film system) between the gates and interconnects to mediate the electrical isolation requirement. The gate structure design, including the specific arrangement of gate electrodes and the dual spacing film configuration, acts as an intermediary solution that prevents direct contact while maintaining high breakdown voltage, thus resolving the contradiction between isolation reliability and voltage strength.
2Strength
If the spacing film is made thicker to increase breakdown voltage, then electrical isolation reliability improves, but device area increases
Solution Approach 1:
The patent applies local quality by making the first spacing film thicker in regions where high breakdown voltage is critical (between gates and interconnects), while maintaining a more compact overall structure. The first spacing film is formed with a thickness greater than that of the second spacing film, concentrating the voltage-blocking function where it is most needed, thus achieving high breakdown voltage without proportionally increasing the overall device area.
Solution Approach 2:
The patent transitions from a single-layer spacing structure to a multi-layer, multi-dimensional spacing film configuration. By stacking the first and second spacing films in different spatial arrangements and thicknesses, the patent achieves high breakdown voltage in the vertical dimension while maintaining compact footprint in the horizontal dimension, effectively resolving the area-voltage trade-off.
3Ease of manufacture
If a conventional single-layer spacing structure is used, then manufacturing process is simple, but breakdown voltage between gates cannot be sufficiently maintained
Solution Approach 1:
The patent employs preliminary action by forming the first spacing film before forming the second spacing film, and by pre-configuring the gate structure with specific electrode arrangements. This sequential formation allows each layer to be optimized independently while maintaining overall process simplicity, achieving high breakdown voltage without requiring complex simultaneous manufacturing steps.
Solution Approach 2:
The patent segments the spacing function into two distinct manufacturing steps: forming the first spacing film with greater thickness for voltage blocking, and forming the second spacing film for additional isolation and structural support. This segmentation maintains manufacturing simplicity by using standard sequential deposition and etching processes, while achieving the high breakdown voltage performance that would be difficult with a single-layer structure.
Data Source
AI summary
A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.