3D Nonvolatile Memory Gate Electrodes With Supporters for Defect Control
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Solution Overview
Problem
Existing three-dimensional nonvolatile memory devices face challenges in reducing gate electrode resistance and preventing process defects, which affect their performance and reliability.
Innovation Solution
The proposed solution involves a nonvolatile memory device design with gate electrodes stacked on a semiconductor substrate, where supporters made of dielectric or semiconductor material penetrate the gate electrodes, reducing resistance by using metal materials for certain electrodes and maintaining spacing with dielectric supporters, and a fabrication method that includes forming active pillars and conductive patterns to prevent defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate electrodes are made thicker to reduce resistance, then electrical conductivity improves, but device area increases and integration density decreases
Solution Approach 1:
The gate electrode uses a composite structure with a first conductive material (e.g., doped polysilicon) and a second conductive material (e.g., metal layer) stacked together. This composite configuration provides high electrical conductivity to reduce resistance while maintaining a compact footprint, resolving the contradiction between conductivity improvement and area minimization.
2Productivity
If gate electrodes are stacked closer together to increase integration, then device density improves, but process defects increase due to spacing constraints
Solution Approach 1:
A dielectric supporter structure is introduced as an intermediary element between adjacent gate electrodes. This supporter maintains precise spacing and alignment, enabling high integration density while preventing process defects such as misalignment or bridging that would occur with closer spacing alone.
3Reliability
If metal materials are used for gate electrodes to reduce resistance, then electrical performance improves, but manufacturing complexity increases
Solution Approach 1:
The gate electrode is segmented into multiple functional layers: a first conductive layer (doped polysilicon) providing structural foundation and a second conductive layer (metal) providing low-resistance electrical pathways. This segmentation allows each layer to be optimized independently, achieving high electrical performance while using established multi-layer fabrication processes.
4Reliability
If dielectric supporters are added to maintain spacing, then process defect prevention improves, but device complexity increases
Solution Approach 1:
The dielectric supporter structure serves multiple functions simultaneously: it maintains spacing between gate electrodes, provides alignment references for subsequent patterning steps, and acts as an insulating barrier. This multi-functionality reduces process defects without adding proportional complexity, as a single structural element accomplishes multiple objectives.
Data Source
AI summary
A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.