3D Memory Gate Stack Layout for Reliable Channel Pillar Conduction
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Solution Overview
Problem
Current semiconductor devices with three-dimensional stacked structures face challenges in improving driving reliability due to limitations in the operational reliability of gate stack structures and manufacturing methods.
Innovation Solution
The semiconductor device incorporates a well structure with channel pillars and a gate stack structure, featuring a slit and select channel pattern to enhance contact and reliability, along with a method involving sacrificial layers, stack formation, and selective etching to create a horizontal space and source junction, improving the integration and reliability of memory strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a three-dimensional stacked gate structure is used to increase integration density, then device capacity and miniaturization are improved, but manufacturing precision and operational reliability deteriorate
Solution Approach 1:
The device is divided into multiple gate stacks (first gate stack, second gate stack, third gate stack) arranged in a three-dimensional configuration. Each gate stack is formed as a separate structural unit with channel regions between them, allowing independent formation and control. This segmentation enables the complex three-dimensional structure to be manufactured through systematic, repeatable processes while maintaining precision.
Solution Approach 2:
Source and drain regions are formed in advance within the channel regions before the final gate electrode structures are completed. The source/drain regions are preliminarily positioned and structured, providing a foundation that guides subsequent gate formation processes. This preliminary action ensures that when gates are stacked three-dimensionally, the underlying channel structures are already in place to maintain alignment and precision.
2Productivity
If gates are stacked on each other for high integration density, then device capacity increases, but operational reliability worsens
Solution Approach 1:
Different regions of the device are given different properties: channel regions are doped with first conductivity type impurities, while source and drain regions are doped with second conductivity type impurities. The gate electrodes are positioned at different heights and locations to create localized control zones. This local differentiation allows each region to be optimized for its specific function, improving overall operational reliability while maintaining high integration density.
Solution Approach 2:
The gate structures are arranged in three dimensions with multiple gate stacks positioned at different heights and lateral locations. The first, second, and third gate stacks are stacked vertically and horizontally, creating a multi-dimensional control architecture. This dimensional expansion allows more comprehensive control over the channel regions, improving reliability by providing multiple control points rather than relying on a single planar gate layer.
3Reliability
If source and drain regions are formed in channel regions with specific doping, then current control is improved, but manufacturing complexity increases
Solution Approach 1:
The formation of source and drain regions is merged with the channel region preparation process. Both the channel regions and source/drain regions are formed within the same semiconductor substrate using coordinated doping steps. The first conductivity type doping for channels and second conductivity type doping for sources/drains are integrated into a unified manufacturing sequence, reducing the number of separate process modules needed and simplifying overall manufacturing complexity.
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.