3D Memory Gate Stack Stabilization With Dummy Pillar Structure
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Solution Overview
Problem
The existing semiconductor memory devices face challenges in reducing structural defects, particularly in the manufacturing process of three-dimensional semiconductor memory devices.
Innovation Solution
The proposed semiconductor memory device includes a gate stack structure with interlayer insulating layers and conductive patterns alternately stacked, a dummy stack structure with dummy interlayer insulating layers and sacrificial layers, a channel structure penetrating the gate stack, a memory layer between the conductive patterns and the channel structure, and a dummy pillar penetrating the dummy stack structure with a length less than the channel structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of memory cells stacked in vertical direction is increased to improve degree of integration, then productivity and integration density improve, but structural defects increase and manufacturing stability deteriorates
Solution Approach 1:
A dummy pillar structure is introduced as an intermediary element between the gate stack structure and the substrate. This dummy pillar includes a filler pattern that fills the space between the gate stack structure and the substrate, acting as a mediator to distribute mechanical stress and prevent structural defects during the stacking process, thereby enabling higher integration without compromising reliability
2Productivity
If complex three-dimensional structures are formed to increase memory cell density, then degree of integration improves, but manufacturing precision and process stability deteriorate
Solution Approach 1:
The dummy pillar structure is formed in advance before the final memory cell stacking is completed. The filler pattern is deposited and planarized beforehand to create a stable foundation, allowing subsequent stacking processes to proceed with higher precision and stability, thus improving manufacturing precision while maintaining high memory cell density
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes: a gate stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns, which are alternately stacked in a vertical direction; a dummy stack structure including a plurality of dummy interlayer insulating layers and a plurality of sacrificial layers, which are alternately stacked in the vertical direction, the dummy stack structure being disposed at a level at which the gate stack structure is disposed; a channel structure penetrating the gate stack structure; a memory layer disposed between each of the plurality of conductive patterns and the channel structure; and a dummy pillar penetrating a portion of the dummy stack structure with a length less than a length of the channel structure in the vertical direction.