3D Memory Gate Stack Contact Isolation for Higher Word-Line Density
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Solution Overview
Problem
The manufacturing processes of three-dimensional semiconductor memory devices become increasingly complex with the stacking of more word lines, making it difficult to improve integration density effectively.
Innovation Solution
A semiconductor memory device design that includes a substrate with a peripheral circuit, a gate stack structure, a channel structure, a memory layer surrounding the channel structure, and a contact plug with an insulating structure to isolate it from the gate stack, along with a method of forming these structures in a way that simplifies the manufacturing process by using interlayer insulating and sacrificial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines stacked on top of each other is increased to improve integration density, then the integration density is improved, but the manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming preliminary structures with first and second semiconductor patterns, building stack structures with alternating interlayer insulating layers and sacrificial layers, creating channel holes and contact holes, depositing memory layers, and replacing sacrificial layers with conductive patterns. This segmentation allows complex 3D structures to be built systematically without overwhelming process complexity
Solution Approach 2:
Preliminary structures including first and second semiconductor patterns separated by insulating layers are formed before the main stack structure is built. Sacrificial layers are pre-positioned within the stack structure to guide subsequent hole formation and material deposition. These preliminary actions simplify later manufacturing steps by establishing a structured framework in advance
2Productivity
If more word lines are stacked to improve integration density, then the integration density is improved, but the manufacturing process becomes more complicated
Solution Approach 1:
Sacrificial layers serve as intermediary structures that facilitate the manufacturing process. These temporary structures guide the formation of channel holes and contact holes, and are later replaced by conductive patterns. The intermediary sacrificial layers enable precise positioning of subsequent materials without requiring complex direct patterning processes
Solution Approach 2:
The structure employs nested layers where interlayer insulating layers and sacrificial layers are alternately stacked to form the stack structure. Channel holes and contact holes are nested within this stack, and memory layers are deposited on the surfaces of these holes. This nested arrangement allows multiple functional elements to be integrated in a compact, systematic manner
Data Source
AI summary
A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.