3D Memory Gate Stack Sidewall Roughness for Stable Integration
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Solution Overview
Problem
As the number of stacked memory cells in three-dimensional semiconductor memory devices increases, the process stability deteriorates, leading to integration challenges.
Innovation Solution
A semiconductor memory device with a gate stacked structure featuring a cell array region and a contact region, where the roughness of the sidewall in the cell array region is higher than that in the contact region, and a vertical structure with depressions and protrusions, along with a method of manufacturing involving the formation of slits and trenches to enhance pattern regularity and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of stacked memory cells is increased to improve integration density, then integration density is improved, but process stability deteriorates
Solution Approach 1:
The gate stacked structure is divided into a cell array region and a contact region with different sidewall roughness characteristics. This segmentation allows each region to be optimized independently: the cell array region has higher roughness for better memory cell formation, while the contact region has lower roughness for improved contact stability and reduced process variability.
Solution Approach 2:
Different regions of the gate stacked structure are given different local qualities through controlled sidewall roughness. The cell array region maintains higher roughness to preserve memory cell performance, while the contact region is specifically treated to have lower roughness for enhanced process stability and reduced stress during manufacturing.
2Productivity
If the number of stacked memory cells is increased to improve integration density, then integration density is improved, but pattern distortion increases
Solution Approach 1:
The gate stacked structure is divided into a cell array region and a contact region with different sidewall roughness characteristics. This segmentation allows each region to be optimized independently: the cell array region has higher roughness for better memory cell formation, while the contact region has lower roughness for improved contact stability and reduced process variability.
Solution Approach 2:
Different regions of the gate stacked structure are given different local qualities through controlled sidewall roughness. The cell array region maintains higher roughness to preserve memory cell performance, while the contact region is specifically treated to have lower roughness for enhanced process stability and reduced stress during manufacturing.
3Productivity
If the number of stacked memory cells is increased to improve integration density, then integration density is improved, but stress on the stacked structure increases
Solution Approach 1:
Different regions of the gate stacked structure are given different local qualities through controlled sidewall roughness. The cell array region maintains higher roughness to preserve memory cell performance, while the contact region is specifically treated to have lower roughness for enhanced process stability and reduced stress during manufacturing.
Solution Approach 2:
The contact region acts as an intermediary between the high-stress cell array region and the substrate. By providing a smoother sidewall surface in this intermediate zone, stress and mechanical instability are reduced, allowing the overall structure to support higher integration densities without compromising structural integrity.
Data Source
AI summary
A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stacked structure with a cell array region and a contact region with a stepped shape, and a roughness of a first sidewall of the cell array region is greater than that of a second sidewall of the contact region.