3D Memory Gate Stack Sidewall Layout for Stable High Cell Density
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Solution Overview
Problem
As the number of stacked memory cells in three-dimensional semiconductor memory devices increases, the process stability deteriorates, leading to integration density challenges.
Innovation Solution
A semiconductor memory device with a gate stacked structure featuring a cell array region and a contact region, where the roughness of the first sidewall of the cell array region is higher than that of the second sidewall of the contact region, and includes a vertical structure with depressions and protrusions facing cell plugs, along with a method of manufacturing that involves forming a slit by coupling auxiliary holes and trenches to improve pattern regularity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked memory cells is increased to improve integration density, then integration density is improved, but process stability deteriorates
Solution Approach 1:
The gate stacked structure is divided into two distinct regions: a cell array region with higher sidewall roughness and a contact region with lower sidewall roughness. This segmentation allows different portions of the structure to have optimized characteristics for their specific functions, enabling higher integration density while maintaining process stability in the contact region.
Solution Approach 2:
Different sidewall roughness characteristics are applied to different regions of the gate stacked structure. The cell array region has higher sidewall roughness to accommodate more memory cells, while the contact region has lower sidewall roughness to ensure process stability and reliable electrical contact. This local differentiation resolves the contradiction between integration density and process stability.
2Quantity of substance
If the number of stacked memory cells is increased to improve integration density, then integration density is improved, but pattern distortion increases
Solution Approach 1:
The gate stacked structure is segmented into cell array and contact regions with different sidewall roughness. The contact region's smoother sidewalls maintain pattern regularity and manufacturing precision, while the cell array region's rougher sidewalls enable higher integration density through increased cell stacking.
Solution Approach 2:
Local quality differentiation in sidewall roughness allows the contact region to maintain high manufacturing precision with smooth sidewalls, while the cell array region achieves high integration density with rougher sidewalls. This resolves the contradiction between pattern regularity and integration density.
3Quantity of substance
If the number of stacked memory cells is increased to improve integration density, then integration density is improved, but stress on the structure increases
Solution Approach 1:
The gate stacked structure is divided into cell array and contact regions. The contact region with smoother sidewalls provides a stable base that reduces structural stress, while the cell array region with rougher sidewalls accommodates higher integration density. This segmentation allows stress distribution that supports both high density and structural integrity.
Solution Approach 2:
Different sidewall roughness in different regions helps manage structural stress. The smoother contact region provides mechanical stability and stress relief, while the rougher cell array region maintains high integration density. This local quality variation resolves the contradiction between integration density and structural stress.
Data Source
AI summary
A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stacked structure with a cell array region and a contact region with a stepped shape, and a roughness of a first sidewall of the cell array region is greater than that of a second sidewall of the contact region.