3D Memory Device Gate Line Stacking for Resistance Control
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in enhancing memory density due to limitations in the integration and arrangement of resistance change memory cells, which affect the resistance value control and overall performance.
Innovation Solution
The memory device incorporates a specific arrangement of silicon members, gate lines, and resistance change films, with alternating gate lines and rounded corners to reduce interconnect resistance, suppress signal delay, and enable uniform current flow, while allowing for thicker gate lines to maintain performance without short circuits, and a control circuit to apply different potentials to gate lines for accurate operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If gate lines are made thicker to maintain performance, then signal delay is reduced, but interconnect resistance increases
Solution Approach 1:
The patent transitions from planar gate line arrangement to a three-dimensional stacked configuration with alternating gate lines at different heights. This vertical stacking allows thicker gate lines to be implemented without increasing lateral interconnect resistance, as the alternating pattern creates shorter current paths and reduces resistance accumulation along the interconnect lines.
Solution Approach 2:
The gate lines are segmented into alternating first and second gate lines positioned at different heights. This segmentation allows each gate line to be independently optimized for thickness while maintaining overall system performance. The segmented arrangement breaks the interconnect path into smaller segments, reducing the total resistance impact.
2Quantity of substance
If memory cells are integrated in three dimensions to improve density, then memory density increases, but resistance value control becomes more difficult
Solution Approach 1:
The patent applies different structural configurations to different regions of the memory device. Specifically, alternating gate lines have different thicknesses and positions, creating local variations in the electric field distribution. This local quality approach allows precise control of resistance values in each memory cell region while maintaining high overall density through the three-dimensional integration.
Solution Approach 2:
The patent varies geometric parameters (gate line thickness, position, and spacing) to control the resistance characteristics of memory cells. By adjusting these parameters in the alternating gate line structure, the invention achieves precise resistance value control despite the complex three-dimensional integration, enabling reliable data storage and retrieval operations.
3Volume of moving object
If gate lines are placed closer together to miniaturize the device, then device size is reduced, but short circuits between gate lines may occur
Solution Approach 1:
The patent resolves the short circuit risk by moving gate lines from a two-dimensional planar arrangement to a three-dimensional stacked configuration. The alternating gate lines are positioned at different heights (vertical separation) in addition to their lateral spacing, creating a three-dimensional separation that prevents short circuits even when lateral spacing is minimized for device miniaturization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances memory density by reducing interconnect resistance, preventing signal delay, and improving breakdown voltage, allowing for the miniaturization of the memory device while maintaining accurate operation and high performance.
Implementation Method 1
Data are stored by controlling the resistance value of this resistance change film
Implementation Method 2
a control circuit to apply different potentials to gate lines for accurate operation
Data Source
AI summary
A memory device includes a first interconnect extending in a first direction, a first and a second semiconductor members extending in a second direction, a first and a second gate lines extending in a third direction, a second and a third interconnects extending in the second direction. The first and the second semiconductor members are arranged along the first direction, with first ends in the second direction connected to the first interconnect. The second interconnect is connected to a second end in the second direction of the first semiconductor member. The third interconnect is connected to a second end in the second direction of the second semiconductor member. The distance between the first interconnect and the first gate line is longer than the distance between the first interconnect and the second gate line.