3D Memory Gate Contacts With Staircase Plugs for Deep Layer Access

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Solution Overview

Problem

The integration limit of semiconductor devices is reached when forming memory cells in a single layer on a substrate, and there is a need for improved operational reliability and stability in three-dimensional semiconductor structures.

Innovation Solution

A semiconductor device with a gate structure comprising alternately stacked conductive and insulating layers, and contact plugs with staircase-shaped sidewalls that extend to different depths and widths, allowing for electrical connections to multiple conductive layers, and a manufacturing method involving polymer layer formation and etching processes to create these plugs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If memory cells are formed in a single layer on a substrate, then the manufacturing process is simpler, but the degree of integration reaches a limit

Engineering Contradiction:
Improvemanufacturing process complexityVSAvoiddegree of integration
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent transitions from two-dimensional single-layer memory cell formation to three-dimensional stacked memory cell structures. Multiple memory cells are vertically stacked to achieve higher integration density while maintaining manufacturing feasibility through sequential formation processes for different cell layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If contact plugs are extended deeper into the gate structure, then electrical connections to multiple conductive layers are improved, but the manufacturing precision becomes more difficult to control

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidcontact plug depth control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The contact plug formation process is segmented into multiple etching stages with different depths. First contact plugs are formed to a first depth, then second contact plugs are formed to a second depth greater than the first depth. This segmentation allows precise control of each contact plug depth independently, ensuring reliable electrical connections to specific conductive layers.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Polymer layers are formed as protective masks before etching the contact holes. The polymer layers are deposited to specific thicknesses that control the etching depth, preventing over-etching and ensuring precise depth control for contact plugs extending into the gate structure.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If the second contact plug extends deeper than the first contact plug, then electrical connection to lower conductive layers is achieved, but the device structure becomes more complex

Engineering Contradiction:
Improveelectrical connection to multiple layersVSAvoidcontact plug structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Different contact plugs are designed with different depths and widths according to their specific electrical connection requirements. The second contact plug extends deeper and has a wider extension portion than the first contact plug, creating locally optimized structures for connecting to different conductive layers without unnecessarily complicating the entire device structure.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances the degree of integration and stability of semiconductor devices by enabling deeper and wider contact plugs, improving the electrical connections and reliability of the device.

Implementation Method 1

extending the first contact hole into the stack by etching the first polymer layer and the stack; and extending the second contact hole into the stack by etching the second polymer layer and the stack

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS20260032908A1Semiconductor device and manufacturing method of semiconductor device
Publication Date: 2026.01.29 SK HYNIX INC
  • US20260032908A1 patent drawing
  • US20260032908A1 patent drawing
  • US20260032908A1 patent drawing

AI summary

A semiconductor device may include a gate structure including conductive layers and insulating layers that are alternately stacked; a first contact plug including a first main portion extended by a first depth through the gate structure and a first extension portion connected to the first main portion and having a sidewall with a staircase shape, the first contact plug being electrically connected to a first conductive layer of the conductive layers; and a second contact plug including a second main portion extended by a second depth greater than the first depth through the gate structure and a second extension portion connected to the second main portion and having a sidewall with a staircase shape, the second contact plug being electrically connected to a second conductive layer of the conductive layers, wherein the second extension portion may have a greater width than the first extension portion.