Non-Volatile Memory Gate Stack for Step Height Integration
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Solution Overview
Problem
In semiconductor manufacturing, the integration of non-volatile memory cells and peripheral logic circuits faces challenges due to height differences in interlayer dielectric layers, affecting chemical mechanical polishing and requiring additional lithography operations to manage step heights and placement of devices.
Innovation Solution
A method is introduced where a substrate is etched to create a step between non-volatile memory cell and peripheral logic circuit areas, allowing for a stacked structure with polysilicon layers and dielectric layers, and metal gates are formed to reduce contact resistance and minimize lithography operations by avoiding dummy structures at the transition area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stacked structure with polysilicon layers and dielectric layers is used to form metal gates, then contact resistance is reduced, but device complexity increases
Solution Approach 1:
The gate structure is segmented into multiple functional layers: a first polysilicon layer forms the control gate, a second polysilicon layer forms the floating gate, and dielectric layers are interspersed between them. This segmentation allows each layer to perform its specific function independently, reducing contact resistance while maintaining manageable complexity through modular construction.
Solution Approach 2:
The patent implements a nested structure where the floating gate (second polysilicon layer) is positioned within the vertical stack between the control gate and the memory cell, with dielectric layers nested between conductive layers. This nesting approach consolidates multiple functions into a compact vertical arrangement, reducing contact resistance without proportionally increasing horizontal device complexity.
2Shape
If substrate etching is performed to create steps between memory cell and logic circuit areas, then height differences are managed, but manufacturing precision requirements increase
Solution Approach 1:
The substrate is selectively etched to create localized steps only in specific regions where memory cells interface with logic circuits. By applying the etching process locally rather than uniformly across the entire substrate, the patent manages height differences at critical interfaces while maintaining standard manufacturing precision requirements for the majority of the device area.
Solution Approach 2:
The substrate etching to create steps is performed as a preliminary action before forming the stacked polysilicon and dielectric structure. By preparing the stepped substrate surface in advance, the patent establishes the necessary height differential management before subsequent layer deposition, thereby reducing the precision requirements for later manufacturing steps.
3Productivity
If dummy structures are avoided at the transition area, then lithography operations are minimized, but device performance consistency becomes more difficult to maintain
Solution Approach 1:
The stacked structure of polysilicon layers and dielectric layers serves multiple functions simultaneously: it forms the metal gate for transistor operation, manages the height transition between memory and logic areas, and provides electrical isolation. By eliminating the need for separate dummy structures, the patent maintains performance consistency through the inherent design of this multi-functional structure while reducing lithography operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance and minimizes the increase in lithography operations, ensuring consistent performance across the semiconductor device by addressing height differences and optimizing the manufacturing process.
Implementation Method 1
A substrate is etched to create a step between non-volatile memory cell and peripheral logic circuit areas
Implementation Method 2
metal gates are formed to reduce contact resistance
Data Source
AI summary
A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.