Memory System Low Power Input Gating Circuitry

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Solution Overview

Problem

Integrated circuits consume significant power due to toggling of control input pins even when in standby or disabled mode, which is not efficiently addressed by existing technologies.

Innovation Solution

The implementation of low power input gating circuitry that includes a chip enable device, latch enable device, latch device, decoder device, and memory device, which uses a latch enable signal to selectively cutoff toggling of the clock input signal to the control input of the memory, reducing power consumption by gating off latches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If memory system operates in active mode with control input pins enabled, then data access performance is improved, but power consumption increases significantly

Engineering Contradiction:

Improvedata access performanceVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent applies dynamics by making the memory system's operational state changeable between active and standby modes. The control input pins are dynamically enabled or disabled based on operational requirements, allowing the system to adapt its power consumption characteristics while maintaining data access capability when needed.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent implements periodic action through alternating between active and standby operational states. The memory system periodically transitions to standby mode to reduce power consumption and returns to active mode when data access is required, creating a rhythmic pattern of high-performance/high-power and low-power states.

Inventive Principle:

Principle #19Periodic action

2Use of energy by moving object

If memory system transitions to standby mode to reduce power consumption, then power usage decreases, but data access capability is reduced

Engineering Contradiction:

Improvepower consumptionVSAvoiddata access capability

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent applies preliminary action by preparing the memory system for standby mode in advance. Control input pins are disabled before actual standby operation begins, and necessary data or states are pre-saved or cached, allowing the system to quickly transition to a low-power state without losing data access capability entirely.

Inventive Principle:

Principle #10Preliminary action

3Speed

If control input pins are continuously enabled for fast data access, then data access speed is maintained, but parasitic power consumption increases

Engineering Contradiction:

Improvedata access speedVSAvoidparasitic power consumption

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The patent extracts or removes the enabling signal from control input pins during standby periods. By taking out the continuous enable signal and replacing it with a gated control mechanism, the system eliminates parasitic power consumption associated with continuously enabled pins while preserving the ability to quickly re-enable them when data access is needed.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS10020031B2Location-based optimization for memory systems

Publication Date: 2018.07.10 ARM LTD

AI summary

Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.