Memory Sub-System Garbage Collection With Separate Read-Write Cores

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Solution Overview

Problem

Traditional memory sub-systems with a single processing core experience performance loss and increased latency during garbage collection procedures due to overhead and processing time inefficiencies, leading to impaired read, write, and erase speeds.

Innovation Solution

Implementing separate processing cores for garbage collection procedures in the memory sub-system, allowing operations to be performed in parallel, with one core handling read processes and another handling write processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single processing core is used for garbage collection procedures, then device complexity is reduced, but processing time and latency increase

Engineering Contradiction:
Improveprocessing core structureVSAvoidgarbage collection latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent divides the garbage collection process into separate stages handled by different processing cores: a first processing core executes read operations to identify valid data, while a second processing core executes write operations to relocate valid data. This segmentation allows parallel execution, reducing the overall garbage collection time and latency while maintaining manageable complexity through specialized core allocation.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If a single processing core handles all garbage collection operations sequentially, then ease of operation is maintained, but productivity decreases

Engineering Contradiction:
Improvecontrol simplicityVSAvoidgarbage collection throughput
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The garbage collection workload is segmented between multiple processing cores with distinct responsibilities. The first core focuses on read operations and valid data identification, while the second core handles write operations and data relocation. This segmentation enables parallel processing that significantly improves throughput while the controller manages coordination between cores, maintaining operational simplicity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

By distributing garbage collection tasks across multiple cores that can operate simultaneously, the system maintains continuous useful action during the garbage collection process. The first core can perform read operations while the second core performs write operations in parallel, eliminating sequential bottlenecks and maintaining productive operation throughout the garbage collection cycle.

Inventive Principle:
Principle #20Continuity of useful action

3Speed

If separate processing cores are implemented for parallel garbage collection, then processing speed improves, but device complexity increases

Engineering Contradiction:
Improvegarbage collection processing speedVSAvoidmulti-core architecture
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent implements separate processing cores with specialized functions: a first processing core dedicated to read operations and valid data identification, and a second processing core dedicated to write operations and data relocation. This segmentation enables parallel execution that improves processing speed while the architectural design keeps complexity manageable by assigning specific tasks to specific cores.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The processing cores are designed with universal capabilities to handle garbage collection operations, where each core can be configured for specific read or write tasks as needed. This multi-functionality approach allows the system to achieve parallel processing speeds while maintaining flexibility and managing complexity through reusable core designs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12468625B2Separate cores for media management of a memory sub-system
Publication Date: 2025.11.11 MICRON TECHNOLOGY INC
  • US12468625B2 patent drawing
  • US12468625B2 patent drawing
  • US12468625B2 patent drawing

AI summary

Methods, systems, and devices for separate cores for media management of a memory sub-system are described. A controller of a memory sub-system can include a first processing core and a second processing core for a garbage collection procedure. The first processing core can perform a first set of one or more operations associated with a read process of a first stage of a garbage collection procedure for a plurality of transfer units of the memory sub-system. The second processing core can perform a second set of one or more operations associated with a write process of the first stage of the garbage collection procedure, where the second set of one or more operations are concurrent with the first set of one or more operations.