3D Nonvolatile Memory GIDL Erase Control for Hot Carrier Reduction
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Solution Overview
Problem
The gate-induced drain leakage (GIDL) erase scheme in three-dimensional nonvolatile memory devices leads to the generation of hot carriers, which degrade the on-off characteristics of selection transistors due to channel gradient distortion.
Innovation Solution
The nonvolatile memory device adjusts erase conditions, such as the slope of the erase voltage and the floating time of row lines, based on the number of program/erase cycles to prevent or reduce the generation of hot carriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If GIDL erase scheme is used in 3D nonvolatile memory device, then erase operation can be performed, but hot carriers are generated causing reduction of on-off characteristic of selection transistor
Solution Approach 1:
The patent applies dynamics by making the erase voltage application timing and row line floating time adjustable based on the number of program/erase cycles. The control logic dynamically modifies the erase operation parameters - specifically, it adjusts when the erase voltage is applied to the bit line or common source line and how long row lines are floated, depending on whether the current cycle is odd or even, thereby adapting the erase process to prevent hot carrier generation while maintaining erase capability
Solution Approach 2:
The patent changes operational parameters to resolve the contradiction. It modifies the erase voltage slope and the floating time of row lines based on the number of executed program/erase cycles. By changing these parameters dynamically - such as adjusting the rise time of erase voltage and the duration of row line floating state - the patent prevents hot carrier generation while maintaining effective erase operation
2Productivity
If erase voltage is applied to perform erase operation, then data can be erased, but hot carriers are generated reducing transistor performance
Solution Approach 1:
The patent implements periodic action by alternating the erase operation method based on the number of program/erase cycles. For odd-numbered cycles, erase voltage is applied to the bit line with specific row line configurations; for even-numbered cycles, erase voltage is applied to the common source line with different row line configurations. This periodic alternation prevents continuous hot carrier generation at the same location while maintaining erase effectiveness
Solution Approach 2:
The patent applies preliminary action by controlling the timing and sequence of voltage application before the actual erase process. The control logic determines in advance whether to apply erase voltage to bit line or common source line based on the cycle number, and pre-configures the row line states (floating or grounded) before applying the erase voltage, thereby preventing hot carrier generation from the outset
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the on-off characteristics of selection transistors and extends the lifetime of the memory device by minimizing channel gradient distortions and hot carrier generation.
Implementation Method 1
a gate induced drain leakage (GIDL) erase scheme is being developed as one of erase schemes for the 3D nonvolatile memory device
Implementation Method 2
the GIDL erase scheme may cause reduction of an on-off characteristic of a selection transistor, due to the generation of hot carriers
Data Source
AI summary
Disclosed is a memory device which a memory cell array including a plurality of memory blocks, a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block from among the plurality of memory blocks, in which an erase operation is to be performed, and control logic configured to control the memory cell array and the voltage generator. The voltage generator is configured to provide the erase voltage to at least one of a bit line and a common source line connected with the target block and to provide the row line voltages to row lines connected with the target block, and the control logic is configured to change a slope of the erase voltage and a floating time of at least one row line among the row lines depending on a program/erase cycle.