Nonvolatile Memory Device Global Line Resistance Equalization
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Solution Overview
Problem
Conventional nonvolatile memory devices fail to apply a voltage independent of memory cell position during write or read operations, leading to varying resistance values in the current path and subsequent voltage drops, affecting the accuracy of data storage and retrieval.
Innovation Solution
The nonvolatile memory device design includes global word and bit lines with equal resistance per unit length and cross-sectional area, formed in the same layer and using the same material as the standard lines, ensuring a consistent voltage application to selected memory cells by equalizing resistance values in the current path, regardless of cell position, through strategically positioned end portions for signal input.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are connected between word lines and bit lines in conventional nonvolatile memory devices, then the memory device can perform write and read operations, but the voltage applied to selected memory cells varies depending on their positions due to varying resistance values in the current path
Solution Approach 1:
The patent applies local quality by making the global word line and global bit line have equal cross-sectional areas to word lines and bit lines, respectively. This creates localized resistance matching at specific points in the circuit, ensuring that the resistance from any memory cell to the signal input end is equalized, thereby achieving position-independent voltage application.
Solution Approach 2:
The patent changes the physical parameters of the global word line and global bit line by setting their cross-sectional areas equal to those of the word lines and bit lines. This parameter adjustment equalizes the resistance values in the current paths, ensuring consistent voltage application to memory cells regardless of their positions.
2Device complexity
If global word line and global bit line have different resistance per unit length, then the device structure can be simplified, but voltage drops occur due to varying resistance values in the current path
Solution Approach 1:
The patent applies local quality by making the global word line and global bit line have equal cross-sectional areas to word lines and bit lines, respectively. This creates localized resistance matching at specific points in the circuit, ensuring that the resistance from any memory cell to the signal input end is equalized, thereby achieving position-independent voltage application.
Solution Approach 2:
The patent changes the physical parameters of the global word line and global bit line by setting their cross-sectional areas equal to those of the word lines and bit lines. This parameter adjustment equalizes the resistance values in the current paths, ensuring consistent voltage application to memory cells regardless of their positions.
Data Source
AI summary
According to one embodiment, a nonvolatile memory device includes first and second word lines, first and second bit lines, memory cells each including a resistance change memory element, a global word line including a first global word line portion including a first end portion, a global bit line including a first global bit line portion including a second end portion. The first and second word lines and the first global bit line portion have a first line width and a first line thickness, the first and second bit lines and the first global word line portion have a second line width and a second line thickness.