Memory Grading via Variable Halting Time for Reliability Assessment

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Solution Overview

Problem

Conventional memory grading methods require multiple costly test environments to ensure operational stability in different environments, which is inefficient and resource-intensive.

Innovation Solution

A method that grades memory by using different halting time periods between electrical charging operations to assess data retention and environmental stability, allowing for testing under a single environment by performing reliability tests that include data-writing, halting, and integrity checks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple different test environments are prepared for performing respective grading tests for different grades, then the memory can be tested for operational stability in different environments, but the cost of maintaining these test environments becomes costly

Engineering Contradiction:
Improveoperational stabilityVSAvoidtesting cost
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent merges multiple test environments into a single test environment by using different halting time periods between electrical charging operations to represent different environmental conditions. Instead of maintaining separate physical test environments for consumer grade, industrial grade, and gaming grade memories, the invention uses temporal variation (different halting durations) within one environment to simulate various operational conditions, thereby reducing maintenance costs while still enabling comprehensive reliability testing.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If conventional grading methods are employed to test memory in different environments respectively, then functional requirements for different grades can be ensured, but multiple test environments need to be maintained

Engineering Contradiction:
Improveenvironmental adaptabilityVSAvoidtest environment complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent changes the temporal parameter (halting time period between charging operations) to represent different environmental conditions and grade requirements. By varying this single parameter within a unified test environment, the system can assess memory adaptability to different grades (consumer, industrial, gaming) without creating multiple complex physical test environments. The processing unit adjusts the halting time period dynamically to simulate different operational stability requirements.

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If data retaining time is used to test environmental stability, then testing can be performed in a single environment, but the relationship between halting time period and environmental durability must be established

Engineering Contradiction:
Improvetesting costVSAvoiddurability assessment
Core Design Contradiction:
Loss of energyVSDifficulty of detecting and measuring

Solution Approach 1:

The patent implements a feedback mechanism where the processing unit writes test data to the memory, halts electrical charging for a predetermined time period, then reads back the data to verify integrity. The system uses this feedback (whether data remains intact after the halting period) to assess memory durability. By adjusting the halting time period and observing the feedback from data integrity checks, the system can determine the memory's environmental stability and appropriate grade classification without requiring multiple physical test environments.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11488679B1Method for grading a memory
Publication Date: 2022.11.01 TEAM GRP
  • US11488679B1 patent drawing
  • US11488679B1 patent drawing

AI summary

Disclosed is a method for grading memory modules comprising: a testing step which applies at least one test procedure to test a memory, each test procedure is provided with a reliability test; and a grading step which grades the memory into corresponding grade level according to test results of said at least one test procedure, and each test result includes a reliability test result wherein the reliability test has the following steps in sequence: performing a data-writing operation on the memory, wherein the data-writing operation is an operation that writes data to the memory; stopping electric charging the memory; halting a predetermined time period; electric charging the memory; checking data integrity of the memory; and generating the reliability test result according to the data integrity.