Nonvolatile Memory Ground Selection Line Floating Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current nonvolatile memory devices face challenges in efficiently erasing data without disturbing the ground selection transistors during an erase operation, which can lead to reliability issues and data loss.
Innovation Solution
The proposed solution involves a nonvolatile memory device architecture that includes a memory cell array with a substrate bias circuit to apply an erase voltage, an address decoder to manage the ground selection lines based on a counter's count value or substrate voltage, and a program circuit to store time information for precise control of the erase operation, ensuring that the ground selection lines are floated at the appropriate time to prevent erasure of the ground selection transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an erase voltage is supplied to the substrate during an erase operation, then data erasure is achieved, but the ground selection transistors may be disturbed leading to reliability issues
Solution Approach 1:
The patent applies preliminary action by floating the ground selection line before supplying the erase voltage to the substrate. This preliminary floating action prevents the ground selection transistors from being disturbed during the subsequent erase operation, thereby protecting their reliability while maintaining ease of manufacture through a simple sequence control mechanism.
Solution Approach 2:
The patent extracts the ground selection line from the erase operation by floating it, effectively removing it from the voltage distribution path during erasure. This isolation prevents the erase voltage from affecting the ground selection transistors, solving the reliability issue without complicating the manufacturing process.
2Reliability
If the ground selection lines are kept at low voltage during erase operation, then ground selection transistors are protected, but erase operation cannot be completed effectively
Solution Approach 1:
The patent applies dynamics by changing the voltage state of the ground selection line from low voltage to floating state at a specific timing during the erase operation. This dynamic adjustment allows the ground selection transistors to be protected initially while enabling effective erase operation later, thus achieving both reliability and productivity goals.
Solution Approach 2:
The patent uses periodic action by sequentially applying different voltage conditions to the ground selection line during the erase operation. First, a low voltage condition protects the ground selection transistors, then a floating condition enables effective erasure, creating a time-dependent periodic voltage pattern that achieves both protection and efficiency.
3Reliability
If precise control of ground selection line voltage is implemented, then erase disturbance is prevented, but device complexity increases
Solution Approach 1:
The patent implements feedback by using a counter to monitor the timing of the erase operation and automatically controlling the ground selection line voltage based on the count value. This feedback mechanism achieves precise control for preventing erase disturbance without significantly increasing device complexity, as the counter and control logic are integrated into the existing memory controller.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of the nonvolatile memory device by preventing erase disturbance of the memory cells and ground selection transistors, thereby ensuring accurate data erasure and improved device performance.
Implementation Method 1
a substrate bias circuit configured to supply an erase voltage to the substrate during an erase operation
Implementation Method 2
the address decoder is further configured to float the at least one ground selection line when a count value of the counter matches the time information
Data Source
AI summary
A nonvolatile memory device configured to apply a wordline erase voltage to a plurality of wordlines connected to a plurality of memory cells, apply an erase voltage to a substrate where a memory cell string is formed while applying a specific voltage to at least one ground selection line connected to at least one ground selection transistor, and float the at least one ground selection line when a target voltage of the substrate reaches a target voltage.