Semiconductor Memory Ground Transistor Step-Cut Error Prevention

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Solution Overview

Problem

Existing semiconductor memory devices face issues with erroneous writing due to step-cuts in wiring, which can cause multiple blocks to be selected concurrently, leading to reduced yield and increased chip defects.

Innovation Solution

Incorporating a ground transistor or ground switch that ensures all blocks are set as non-selection blocks even in the presence of step-cuts, using a ground transistor with one end connected to ground voltage and the other end connected to the wiring, and a ground switch that constantly connects the wiring to ground, preventing concurrent selection of blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If wiring is used to connect blocks without additional ground connections, then device complexity is reduced, but reliability deteriorates due to erroneous writing caused by step-cuts

Engineering Contradiction:
Improvewriting accuracyVSAvoidwiring structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A ground transistor is introduced as an intermediary component between the wiring and ground. This transistor acts as a mediator that conditionally connects blocks to ground based on selection signals, preventing erroneous writing caused by step-cuts while maintaining normal operation during step-free conditions

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The ground transistor is configured to preemptively prevent erroneous writing by establishing a ground connection before the error can occur. When a step-cut is detected or anticipated, the ground transistor activates in advance to set the affected block as non-selection, preventing the error from propagating

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple blocks are allowed to be selected concurrently, then productivity is improved, but manufacturing precision deteriorates due to erroneous writing to non-selection blocks

Engineering Contradiction:
Improvewriting speedVSAvoidblock selection accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The ground transistor configuration creates a feedback mechanism where the selection state of blocks is continuously monitored and adjusted. When concurrent selection causes erroneous writing to non-selection blocks, the ground transistor receives feedback and adjusts the ground connection to correct the selection error, ensuring only intended blocks are written to

Inventive Principle:
Principle #23Feedback

3Reliability

If ground transistors are added to prevent step-cut errors, then reliability is improved, but device complexity increases

Engineering Contradiction:
ImproveyieldVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Ground transistors are strategically placed only at critical locations where step-cuts are most likely to cause errors, rather than uniformly across all blocks. This localized approach provides reliability improvement where needed while minimizing the overall increase in device complexity

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10083756B2Semiconductor memory device
Publication Date: 2018.09.25 KIOXIA CORP
  • US10083756B2 patent drawing
  • US10083756B2 patent drawing
  • US10083756B2 patent drawing

AI summary

According to one embodiment, a semiconductor memory device includes a row decoder that outputs a first signal to a first wiring and outputs a second signal to a second wiring, a switch that has one end to which a first voltage is supplied, another end connected to the first wiring, and a gate connected to the second wiring, a first transistor and a second transistor that have respective gates connected to the first wiring at connecting positions located between the row decoder and the another end of the switch on the first wiring, a third transistor and a fourth transistor that have respective gates to which signals having opposite logic levels are respectively input, and a driver that is connected to one end of the first transistor via the third transistor and is connected to one end of the second transistor via the fourth transistor.