Memory Group Power Mode Control via Common Chip Enable Signal
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Solution Overview
Problem
Memory systems with multiple logical units (LUNs) experience significant power consumption due to all LUNs in a group entering an elevated power mode when one is activated, even if only one LUN is performing an operation, leading to inefficiency in power usage.
Innovation Solution
Implementing a power management system where unselected LUNs transition to a lower power mode (Mode 2) instead of the elevated power mode (Mode 1), reducing current draw and allowing for faster reactivation when needed, while the selected LUN operates in Mode 1, using a common chip enable signal to control power modes within a memory group.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a common chip enable signal is used to activate all LUNs in a memory group, then the circuit complexity is reduced and layout area is saved, but the power consumption increases significantly because all LUNs enter an elevated power mode even when only one is being accessed
Solution Approach 1:
The patent applies local quality by differentiating the power mode of individual LUNs within the same memory group. While the common CE signal activates all LUNs, the selected LUN enters an elevated power mode (Mode 1) for active operation, while unselected LUNs remain in a lower power mode (Mode 2). This selective power state assignment reduces overall power consumption without requiring separate CE signals for each LUN, thus maintaining circuit simplicity while improving energy efficiency.
2Productivity
If all LUNs in a memory group are activated to an elevated power mode, then all LUNs are ready to perform memory operations, but the current draw becomes additive across all unselected LUNs resulting in significant power consumption
Solution Approach 1:
The patent changes the power mode parameter selectively for different LUNs based on their operational status. The selected LUN transitions to Mode 1 (elevated power mode) to ensure readiness for memory operations, while unselected LUNs remain in Mode 2 (lower power mode). This parameter differentiation allows the system to maintain operational readiness for the active LUN while minimizing the additive current draw from inactive LUNs, thus resolving the contradiction between productivity and energy loss.
3Loss of energy
If unselected LUNs remain in a lower power mode, then power consumption is reduced, but there may be increased latency when these LUNs need to be activated for operations
Solution Approach 1:
The patent applies preliminary action by keeping unselected LUNs in Mode 2, which is an intermediate power state that maintains basic readiness while consuming less power than Mode 1. This preliminary state allows unselected LUNs to be activated more quickly than if they were in a deep sleep mode, thus reducing activation latency when they need to be accessed. The system balances power savings with acceptable latency by using Mode 2 as a preparatory state for potential future operations.
Data Source
AI summary
Disclosed are examples of apparatuses including memory devices and systems comprising memories sharing a common enable signal, wherein the memories may be put into different power modes. Example methods for setting the different power modes of the memories are disclosed. In some examples, different power modes may be set by issuing memory group-level commands, memory-level commands, or combinations thereof.