Memory Device Group-Based Rewrite Logic Circuit
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Solution Overview
Problem
Existing memory devices are inefficient in rewriting failed data bits, as they typically require multiple iterations per data word, consuming time and power, and lack sufficient tolerance for initial write operation errors.
Innovation Solution
Implementing a control logic circuit that groups data words into sets and rewrites failed data bits based on these sets, rather than individual words, allowing for more efficient rewriting and reduced error tolerance in the initial write signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing memory devices rewrite failed data bits based on a unit of a single word with multiple iterations, then the data accuracy is improved, but the time consumption and power consumption increase significantly
Solution Approach 1:
The patent merges multiple data words into a data word group and rewrites failed data bits across the entire group in a single operation rather than processing each word separately. This combining approach reduces the total number of rewrite iterations needed while maintaining data accuracy, directly resolving the contradiction between reliability and time consumption.
Solution Approach 2:
The patent implements a multi-word rewrite mechanism that can handle failed data bits across multiple words simultaneously using a unified rewrite process. This universal approach allows the system to process different data words through the same efficient group-based methodology, reducing overall processing time while ensuring accurate rewriting across all words.
2Reliability
If existing memory devices rewrite failed data bits based on a unit of a single word with multiple iterations, then the data accuracy is improved, but the power consumption increases
Solution Approach 1:
By combining multiple data words into a group and performing a single rewrite operation for all failed bits in the group, the patent reduces the cumulative power consumption that would result from multiple separate rewrite operations on individual words, while still achieving accurate data storage.
Solution Approach 2:
The patent enables continuous processing of multiple data words through group-based rewriting, eliminating the stop-start nature of iterative single-word processing. This continuous approach reduces power consumption by maintaining a more efficient operational state across the entire data word group rather than repeatedly initializing and executing separate rewrite cycles for each word.
3Duration of action of stationary object
If the initial write operation has high error tolerance, then the endurance of memory bit cells is improved, but the data accuracy may be compromised
Solution Approach 1:
The patent performs preliminary verification of data words after the initial write operation to identify failed data bits. This preliminary detection allows the system to use a lower-power, more tolerant initial write signal while ensuring data accuracy through subsequent group-based rewriting of only the failed bits, thus protecting memory cell endurance without sacrificing reliability.
Solution Approach 2:
The patent implements a feedback mechanism where the system verifies the successful writing of data bits and identifies failures. This feedback enables selective rewriting of only the failed data bits in groups, allowing the initial write operation to use higher tolerance signals that preserve memory cell endurance while maintaining overall data accuracy through the feedback-driven correction process.
Data Source
AI summary
A circuit includes: writing a plurality of data words, each of which has a plurality of data bits, into respective bit cells of a memory device; in response to determining that not all the data bits of the plurality of data words are correctly written into the respective bit cells of the memory device, grouping the plurality of data words as a plurality of data word sets; and simultaneously rewriting a subset of data bits that were not correctly written into the respective bit cells of the memory device, wherein the subset of the data bits are contained in a respective one of the plurality of data word sets.