Memory Device Half-Page Mode Power Savings
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Solution Overview
Problem
There is a need to improve the efficiency of memory devices and memory modules by reducing power consumption and allowing for additional information to be stored, particularly in modes where less than all memory cells are accessed at once.
Innovation Solution
The implementation of half-page modes in memory devices, where each word line is divided into separately addressed portions, allows for power savings by activating only the necessary portions of the word line during access operations. Additionally, module parity bits are stored on data memory devices, eliminating the need for error correction memory devices, and additional information such as metadata is transmitted in parallel with data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If half-page mode is implemented with separate word line portions, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent divides each word line into two separately addressable portions (first portion and second portion), allowing independent activation. This segmentation enables the memory device to activate only the necessary portion during access operations, reducing power consumption while managing complexity through systematic organization of the divided structures.
Solution Approach 2:
The patent implements dynamic addressing where the row address includes a row driver select bit that dynamically determines which portion of the word line is activated. This dynamic control allows the system to adapt between accessing different portions based on operational needs, optimizing power usage while maintaining flexible access patterns.
2Device complexity
If module parity bits are stored on data memory devices, then error correction memory devices can be eliminated, but device complexity increases
Solution Approach 1:
The patent combines the functions of data storage and parity bit storage within the same data memory devices. By storing module parity bits associated with data in the data memory devices themselves, the patent eliminates the need for separate error correction memory devices, thereby reducing overall device complexity while maintaining error correction capability.
Solution Approach 2:
The data memory devices are designed to perform multiple functions: storing both data and module parity bits. This multi-functionality allows the same hardware resources to serve dual purposes, eliminating the need for dedicated error correction memory devices and reducing overall system complexity.
3Quantity of substance
If additional information is transmitted in parallel with data, then information storage capacity increases, but data transmission complexity increases
Solution Approach 1:
The patent utilizes an additional dimension in data transmission by incorporating an additional data terminal alongside the existing data terminals. This allows additional information to be transmitted in parallel with data without interfering with the existing data transmission protocol, effectively increasing information capacity while maintaining compatibility with current interfaces.
Solution Approach 2:
The patent introduces an additional data terminal as an intermediary channel for transmitting additional information. This intermediary approach allows parallel transmission of data and additional information without requiring fundamental changes to the existing data transmission mechanism, thereby increasing capacity while managing complexity through additive rather than transformative changes.
Data Source
AI summary
Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.