Multi-Core Memory Handling for Application-Specific Latency
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Solution Overview
Problem
In multi-core processing systems, existing memory handling methods do not effectively optimize latency requirements for individual applications, leading to inefficient resource utilization and increased energy consumption due to a lack of consideration for application-specific latency needs.
Innovation Solution
A method is introduced that detects data access criteria in a multi-core processing system, determines which data is related to specific applications, and allocates memory resources based on cache information to migrate data to optimal memory portions, thereby optimizing data access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in main memory (DRAM) to reduce cost, then memory capacity increases and cost decreases, but data access latency increases significantly
Solution Approach 1:
The memory system is segmented into multiple portions (first memory portion associated with first cache portion, second memory portion associated with second cache portion). This segmentation allows data to be distributed across different memory regions based on access patterns, enabling faster access to frequently used data while maintaining overall memory capacity.
Solution Approach 2:
Data is pre-positioned in optimal memory portions based on predicted access patterns and application requirements. By anticipating which data will be needed and placing it in the appropriate memory portion beforehand, the system reduces access latency without requiring all data to reside in fast cache memory.
2Speed
If memory is organized in hierarchical structure with cache memory, then data access speed improves, but system cost increases due to expensive SRAM
Solution Approach 1:
Different memory portions are assigned different qualities or characteristics based on local access requirements. The first memory portion is optimized for applications requiring fast access (associated with first cache portion), while the second memory portion serves applications with different access patterns. This local optimization allows the system to provide high-speed access where needed without uniformly expensive hardware throughout.
Solution Approach 2:
The memory system provides multiple functions through a unified architecture that can serve both high-speed and capacity-oriented requirements. The same memory controller and interconnect infrastructure supports both the first and second memory portions, allowing the system to function as both a high-performance cache and a large-capacity storage system simultaneously.
3Quantity of substance
If LLC is divided into multiple slices accessible by all cores, then memory capacity per core increases, but access latency varies and cannot meet individual application requirements
Solution Approach 1:
The system performs preliminary analysis of application latency requirements and pre-allocates specific memory portions to applications based on their needs. By determining which applications require low latency and which memory portions can provide that latency beforehand, the system can guarantee performance requirements without requiring all cores to access all memory slices equally.
Solution Approach 2:
The memory controller acts as an intermediary that manages access between processing cores and memory portions. It monitors access patterns, determines optimal memory placement, and routes access requests to appropriate memory portions, thereby reducing latency variability and ensuring individual application requirements are met.
Data Source
AI summary
A method in a multi-core processing system which comprises a processor comprising at least a first and a second processing unit, a cache, common to the first and the second processing unit, comprising a first cache portion associated with the first processing unit and a second cache portion associated with the second processing unit, a memory, comprising a first memory portion associated with the first cache portion and a second memory portion associated with the second cache portion. The method comprises detecting that a data access criteria of the second memory portion is fulfilled, establishing that first data stored in the second memory portion is related to a first application running on the first processing unit, allocating at least a part of the first memory portion to the first application based on cache information, and migrating the first data to the part of first memory portion.