Memory System Hash Addressing for Direct Device Communication

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Solution Overview

Problem

In memory systems with multiple devices, data loading times and power consumption increase due to the need for extensive data transfer and address management, particularly when processing large volumes of data across numerous memory devices.

Innovation Solution

A memory system that enables direct communication between memory devices through a pooled memory controller, using hash addresses to access data packets without designating fixed addresses, thereby reducing data transfer time and power consumption by allowing data to be stored and retrieved efficiently across multiple memory devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If data is transferred between multiple memory devices through a controller with fixed address designation, then data can be accessed in an organized manner, but data transfer time and power consumption increase

Engineering Contradiction:
Improvedata loading timeVSAvoidaddress management complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent extracts the address management function from the controller and replaces it with hash address calculation performed by memory devices themselves. Each memory device calculates hash addresses from header information to determine data storage locations, eliminating the need for complex controller-mediated address management and reducing data loading time.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Memory devices perform self-service by autonomously calculating hash addresses and determining data storage locations without controller intervention. This self-addressing mechanism reduces communication overhead and power consumption while maintaining organized data access across multiple memory devices.

Inventive Principle:
Principle #25Self-service

2Productivity

If direct communication between memory devices is implemented without fixed addresses, then data transfer rate increases, but data access organization becomes more difficult

Engineering Contradiction:
Improvedata transfer rateVSAvoiddata access organization
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The patent changes the addressing parameter from fixed physical addresses to dynamic hash addresses calculated from data header information. This parameter transformation enables direct memory-to-memory communication while maintaining data organization through consistent hash-based address generation, thereby increasing data transfer rate without sacrificing accessibility.

Inventive Principle:
Principle #35Parameter changes

3Quantity of substance

If extensive data transfer across multiple memory devices is performed, then storage capacity increases, but power consumption increases

Engineering Contradiction:
Improvestorage capacityVSAvoidpower consumption
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent introduces hash address calculation as an intermediary mechanism that enables efficient data routing between memory devices. By calculating hash addresses from header information, the system determines data locations without extensive controller-mediated data transfer, reducing power consumption while maintaining access to distributed storage capacity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11288012B2Memory system
Publication Date: 2022.03.29 SK HYNIX INC
  • US11288012B2 patent drawing
  • US11288012B2 patent drawing
  • US11288012B2 patent drawing

AI summary

A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.