Memory System Direct Device Communication Hash Routing
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Solution Overview
Problem
In memory systems with multiple devices, data loading times and power consumption increase due to the need for data communication between a controller and memory devices, especially when handling large volumes of data, as existing systems rely on address designation and sequential data transfer.
Innovation Solution
Implementing a memory system where data packets with header information are directly communicated between memory devices without address designation, using hash addresses to access data stored in different positions, allowing for pseudo-random address allocation and reducing the need for sequential data transfer through the controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data communication is performed through the controller between memory devices, then data transfer can be managed centrally, but data loading time increases rapidly when a large number of memory devices are contained
Solution Approach 1:
The patent introduces a routing mechanism that acts as an intermediary between memory devices, enabling direct peer-to-peer data communication without always routing through the controller. This allows memory devices to exchange data directly when possible, reducing the data loading time while maintaining centralized management capabilities when needed.
Solution Approach 2:
The patent segments the data communication path by allowing multiple direct communication channels between memory devices alongside the controller path. This creates parallel data transfer routes, enabling data to be transferred through the most efficient path and significantly reducing overall data loading time for large numbers of memory devices.
2Productivity
If data communication is performed through the controller between memory devices, then data transfer can be managed centrally, but power consumption increases during data communication
Solution Approach 1:
The routing mechanism enables memory devices to communicate directly without involving the controller for every data transfer operation. This reduces the power consumption associated with controller-mediated communication while maintaining the ability to use the controller when centralized management is required.
Solution Approach 2:
By segmenting communication into direct device-to-device paths and controller-mediated paths, the system can select the lower-power direct path for routine data transfers, thereby reducing overall power consumption during data communication operations.
3Measurement precision
If address designation is used for data transfer, then data can be located precisely, but data transfer requires sequential processing through the controller
Solution Approach 1:
The routing mechanism serves as an intelligent intermediary that uses address information for precise data location while enabling direct communication paths. This eliminates the need for sequential controller processing while maintaining precise data location capabilities through the routing logic.
4Quantity of substance
If a large number of memory devices are contained in the memory system, then storage capacity increases, but data loading time increases rapidly
Solution Approach 1:
The patent segments the memory system into multiple directly-connected memory devices that can communicate in parallel. This segmentation allows the system to scale storage capacity by adding more devices without proportionally increasing data loading time, as data can be retrieved from multiple devices simultaneously through direct communication paths.
Solution Approach 2:
The patent introduces a new communication dimension by establishing direct peer-to-peer connections between memory devices, creating a mesh-like topology rather than a simple linear or star topology through the controller. This dimensional change in communication architecture enables parallel data access and reduces data loading time as the system scales.
Data Source
AI summary
A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.