Memory System with Hashed Packet Routing for Big Data
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Solution Overview
Problem
As the demand for processing big data increases, traditional memory systems face challenges with data loading times and power consumption due to the need for high-capacity memory devices and increased data transfer times when numerous memory devices are used, especially in mobile communication terminals and IoT applications.
Innovation Solution
A memory system that enables direct data communication between memory devices without designating specific addresses, using a pooled memory controller to perform map computations and packet relay through a fabric network, allowing data to be transmitted in a packet format with hashed header information for efficient access and storage across multiple memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large number of memory devices are contained in the memory system to increase storage capacity, then storage capacity is improved, but data loading time increases rapidly
Solution Approach 1:
The memory system is segmented into multiple independent memory devices (first memory device, second memory device, etc.) that can be accessed simultaneously. Each memory device operates independently with its own data lines, allowing parallel data loading operations that reduce overall data loading time while maintaining high storage capacity.
2Quantity of substance
If a large number of memory devices are contained in the memory system to increase storage capacity, then storage capacity is improved, but data transfer time increases
Solution Approach 1:
Data transfer operations are segmented across multiple independent memory devices with separate data lines. This allows simultaneous data transfer to and from different memory devices, reducing overall data transfer time while maintaining high storage capacity.
Solution Approach 2:
The memory controller acts as an intermediary that manages and coordinates data transfer operations across multiple memory devices. It optimizes data flow by directing transfers through appropriate memory devices based on address information, reducing bottlenecks and overall transfer time.
3Quantity of substance
If a large number of memory devices are contained in the memory system to increase storage capacity, then storage capacity is improved, but power consumption increases
Solution Approach 1:
The memory system divides storage capacity across multiple independent memory devices, each with its own control and data lines. This segmentation allows the memory controller to activate only the specific memory devices needed for current operations, reducing overall power consumption compared to a single large memory device that would require full activation.
Solution Approach 2:
Different memory devices can be in different operational states (active, standby, or powered down) based on local access requirements. The memory controller enables selective activation of individual memory devices or groups, allowing parts of the system to consume less power when not currently accessed, while maintaining total storage capacity.
4Productivity
If data is transmitted in packet format with hashed header information, then data access efficiency is improved, but system complexity increases
Solution Approach 1:
The system transforms traditional address-based data access into hash-based packet routing. By changing the addressing parameter from direct memory addresses to hashed header values, the system achieves more efficient data access through the first memory device using hash table lookup, while the packet format encapsulates all necessary routing information.
Solution Approach 2:
The packet format with header information acts as an intermediary that carries routing and identification data between the controller and memory devices. The hashed header serves as a key that the first memory device uses to efficiently locate and retrieve the corresponding data packet, reducing access time while the structured packet format manages the added system complexity.
Data Source
AI summary
A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.