Memory Header Switch Control for Noise-Robust Shutdown
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Solution Overview
Problem
Existing memory devices, such as SRAM, face issues with power switch control, particularly during shutdown modes, where uncontrolled switching procedures can lead to stress on header switches and direct current leakage due to signal noise and long control signal lines, resulting in increased power consumption and reduced reliability.
Innovation Solution
A power switch control circuit is implemented with a state latch and output latch configuration that includes level shifters and NAND gates to manage control signals for PMOS header switches, ensuring they are turned off during shutdown, even in the presence of noise, and reducing DC leakage by using sequential control and feedback mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If header switches are turned off during shutdown mode, then power consumption is reduced, but control signal lines become longer and more susceptible to noise
Solution Approach 1:
The patent introduces intermediary circuits including level shifters and latch circuits between the control signal source and the header switches. These intermediaries condition and strengthen the control signals before they reach the switches, making them more robust against noise while still enabling shutdown mode power savings.
Solution Approach 2:
The control circuit performs preliminary actions by pre-conditioning the shutdown control signal through level shifting and latch circuits before it reaches the header switches. This preliminary strengthening of the control signal ensures noise immunity is established before the switches are actuated, preventing noise-induced false triggering.
2Speed
If power supplies are allowed to short together during switching, then switching speed is improved, but header switches experience stress and reliability decreases
Solution Approach 1:
The control circuit implements beforehand cushioning by using latch circuits that control the timing and sequence of header switch activation. The latches ensure that switches are turned on in a controlled manner with proper timing, preventing direct shorting of power supplies while maintaining fast switching performance through optimized control signal timing.
3Loss of energy
If internal header switches are turned off during shutdown, then power consumption is reduced, but DC leakage increases due to uncontrolled switches
Solution Approach 1:
The control circuit employs feedback mechanisms where the state of the header switches is monitored and fed back to the latch circuits. This feedback ensures that both internal and external header switches are properly controlled to be in the off state during shutdown mode, preventing DC leakage paths while maintaining the power savings from reduced switch operation.
Data Source
AI summary
A power switch control circuit includes a supply rail configured to supply power to a memory array. A first header switch couples the supply rail to a first power supply that corresponds to a first power domain. A second header switch couples the supply rail to a second power supply that corresponds to a second power domain. A control circuit is configured to receive a select signal and a shutdown signal, and to output control signals to the first and second header switches to selectively couple the first and second header switches to the first and second power supplies, respectively, in response to the select signal and the shutdown signal. The control circuit is configured to output the control signals to the first and second header switches to disconnect both the first and second header switches from the first and second power supplies in response to the shutdown signal and irrespective of the select signal.