Memory Structure Hexagonal Active Pillars Storage Density
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Solution Overview
Problem
The increasing demand for higher storage density in memory technologies poses a challenge in integrating memory components effectively, as existing solutions struggle to optimize the arrangement and connectivity of bit lines, active pillars, and capacitors for enhanced performance and density.
Innovation Solution
A memory structure featuring vertically oriented transistors with active pillars arranged in a hexagonal array, connected by bit lines and word lines, and capacitors electrically connected via connecting pads, which allows for a compact and efficient layout that maximizes storage density and reduces contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional memory integration methods are used, then manufacturing process is simpler, but storage density is insufficient
Solution Approach 1:
The patent transitions from planar transistor arrangement to vertical transistor structure, where bit lines extend vertically through multiple layers. This dimensional change allows significantly more capacitors to be packed into the same footprint, achieving higher storage density without proportionally increasing device area complexity.
Solution Approach 2:
The patent implements nested interlayer connections where bit lines are routed through multiple substrate layers with via holes connecting adjacent layers. Capacitors are positioned between word lines in the vertical dimension, creating a nested arrangement that maximizes space utilization and increases storage density.
2Quantity of substance
If component arrangement is optimized for higher density, then storage capacity increases, but contact resistance increases
Solution Approach 1:
The patent introduces connecting pads as intermediary elements between capacitors and bit lines. These connecting pads are specifically designed with low contact resistance to bridge the gap between densely packed components, maintaining signal integrity while enabling high-density arrangement.
Solution Approach 2:
The patent optimizes the geometric parameters of connecting pads and via holes to minimize contact resistance. By carefully controlling the dimensions, materials, and spacing of these interconnection elements, the patent achieves low resistance despite reduced spacing between components.
3Quantity of substance
If vertical transistor structure is implemented, then storage density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the vertical interconnection structure into discrete via holes at regular intervals between bit lines. This segmentation creates a modular pattern that is easier to manufacture with standard lithography, reducing the precision requirements compared to continuous or irregular vertical routing schemes.
Solution Approach 2:
The patent designs the vertical bit lines and word lines to maintain consistent spacing and alignment relationships throughout the structure. This equipotential design approach ensures uniform electrical characteristics and simplifies manufacturing by creating repetitive, predictable patterns that are easier to control.
Data Source
AI summary
A memory includes a substrate; a plurality of bit lines on the substrate, which are parallel to each other and extend in a first direction; a plurality of active pillars on the bit lines, bottom ends of which are connected to the bit lines; a plurality of word lines parallel to each other and extending in a second direction, which surround outer sidewalls of the active pillars, and expose top ends of the active pillars, the active pillars and the word lines jointly constitute vertical memory transistors of the memory; and a plurality of capacitors and a plurality of connecting pads, each of the capacitors is located on each of the active pillars, each of the connecting pads is located between the active pillar and the capacitor.