Computer Memory Management with Hierarchical Metadata

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Solution Overview

Problem

Existing memory management techniques in computing devices with large amounts of memory suffer from significant metadata overhead and high processing latency when allocating large memory blocks, which reduces system performance.

Innovation Solution

Implementing multiple functional types of memory coexisting on a physical memory in a computing device, with concurrent tracking of status for memory subdivisions of different sizes by the operating system, allowing for efficient allocation and deallocation of memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory is subdivided into multiple small pages with individual metadata tracking, then memory allocation flexibility is improved, but metadata overhead increases significantly

Engineering Contradiction:
Improvememory allocation flexibilityVSAvoidmetadata overhead
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent segments memory management into two distinct hierarchies: fine-grained memory pages (4KB) for allocation flexibility and coarse-grained memory blocks (1MB-1GB) for metadata efficiency. Each level has its own metadata structures, allowing the system to track small allocations precisely while reducing overall metadata overhead through block-level aggregation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements a nested metadata structure where block-level metadata contains references to page-level metadata, which in turn contains individual page status information. This nested hierarchy allows the system to manage terabytes of memory with minimal top-level metadata while maintaining detailed tracking capability at lower levels.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Manufacturing precision

If metadata is updated individually for each memory page during allocation, then allocation accuracy is improved, but processing latency increases

Engineering Contradiction:
Improveallocation accuracyVSAvoidprocessing latency
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent pre-allocates contiguous memory blocks in advance and marks them as reserved at the block level without individually tracking each page within the block. When allocation requests arrive, the system quickly identifies available blocks and performs bulk page-level marking, reducing the frequency of individual metadata updates while maintaining allocation accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent merges multiple page-level metadata operations into single block-level operations. When a block is allocated or freed, the system updates the block metadata once rather than individually updating each page metadata, significantly reducing processing latency for large memory allocations while maintaining precise tracking through the nested structure.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12204449B2Computer memory management in computing devices
Publication Date: 2025.01.21 MICROSOFT TECHNOLOGY LICENSING LLC
  • US12204449B2 patent drawing
  • US12204449B2 patent drawing
  • US12204449B2 patent drawing

AI summary

Techniques for computer memory management are disclosed herein. In one embodiment, a method includes in response to receiving a request for allocation of memory, determining whether the request is for allocation from a first memory region or a second memory region of the physical memory. The first memory region has first memory subregions of a first size and the second memory region having second memory subregions of a second size larger than the first size of the first memory region. The method further includes in response to determining that the request for allocation of memory is for allocation from the first or second memory region, allocating a portion of the first or second multiple memory subregions of the first or second memory region, respectively, in response to the request.